US6235567B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Silicon-germanium bicmos on soi
Assignee: GlobalFoundries Inc
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Filing: 1999-08-31
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Granted: 2001-05-22
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Expires: 2019-08-31
Abstract
Abstract A BiCMOS integrated circuit is formed with CMOS transistors on an SOI substrate in a silicon layer having a standard thickness of 0.1 μm to 0.2 μm and with Bipolar SiGe transistors formed in an epitaxial layer nominally 0.5 μm thick. The CMOS transistors are formed first with standard processing, then covered with an insulating film. The insulating film is stripped in the bipolar areas and an epitaxial SiGe layer is deposited on the Si substrate. The bipolar transistors are formed using the SiGe epi layer for the base and having an encapsulated structure for device isolation using shallow isolation trenches and the buried oxide.
Inventors
- 👤 Feng-Yi Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:47
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/201; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; H10D86/01
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
250 words
A method of forming a BiCMOS integrated circuit containing bipolar transistors in a bipolar region and CMOS transistors in a CMOS region, comprising the steps of: preparing an SOI silicon substrate above an insulating buried layer, said silicon substrate having a crystalline silicon device layer with a device layer top surface and having a CMOS transistor thickness; depositing an epitaxial layer of silicon, having an epitaxial layer top surface on said crystalline silicon device layer top surface; removing said epitaxial layer of silicon above said CMOS area; forming a set of shallow isolation trenches about transistor sites in said CMOS region; forming a set of CMOS transistors, having CMOS transistor gates with a top surface, in said transistor sites; depositing an insulating layer, having an insulating layer top surface, above said device layer in said CMOS region, thereby filling in said set of shallow isolation trenches and areas between said CMOS transistors in said CMOS region; planarizing said insulating layer and said epitaxial layer so that said epitaxial layer top surface and said insulating layer top surface are substantially coplanar; forming a set of isolation trenches in said epitaxial layer for isolating terminals of said bipolar transistors; depositing a layer of SiGe alloy above said epitaxial layer; forming a set of bipolar transistors using said portions of said epitaxial layer as collectors and portions of said layer of SiGe alloy as bases in said bipolar region; and connecting said CMOS transistors and said bipolar transistors to form said integrated circuit.
Claim 2
Independent Claim
250 words
A method of forming a BiCMOS integrated circuit containing bipolar transistors in a bipolar region and CMOS transistors in a CMOS region, comprising the steps of: preparing an SOI silicon substrate above an insulating buried layer, said silicon substrate having a crystalline silicon device layer with a device layer top surface and having a CMOS transistor thickness; depositing an epitaxial layer of silicon, having an epitaxial layer top surface on said crystalline silicon device layer top surface; removing said epitaxial layer of silicon above said CMOS area; forming a set of shallow isolation trenches about transistor sites in said CMOS region; forming a set of CMOS transistors, having CMOS transistor gates with a top surface, in said transistor sites; depositing an insulating layer, having an insulating layer top surface, above said device layer in said CMOS region, thereby filling in said set of shallow isolation trenches and areas between said CMOS transistors in said CMOS region; planarizing said insulating layer and said epitaxial layer so that said epitaxial layer top surface and said insulating layer top surface are substantially coplanar; forming a set of isolation trenches in said epitaxial layer for isolating terminals of said bipolar transistors; depositing a layer of SiGe alloy above said epitaxial layer; forming a set of bipolar transistors using said portions of said epitaxial layer as collectors and portions of said layer of SiGe alloy as bases in said bipolar region; and connecting said CMOS transistors and said bipolar transistors to form said integrated circuit.
Claim 3
Dependent Claim
39 words
A method according to claim 1 , in which said step of forming a set of shallow isolation trenches about transistor sites and said step of forming a set of isolation trenches in said epitaxial layer are performed simultaneously.
Claim 4
Dependent Claim
40 words
A method according to claim 2 , in which silicon contact areas of said CMOS transistors and said bipolar transistors are exposed, a layer of metal is deposited and heated to form self-aligned silicide with said exposed silicon contact areas.
Claim 5
Dependent Claim
60 words
A method according to claim 3 , in which at least one of said collectors is disposed over said insulating buried layer and bounded by shallow isolation trenches, thereby forming an epitaxial collector block and in which said insulating layer surrounds said epitaxial collector block, whereby said epitaxial collector block is encapsulated in insulator and isolated from said silicon substrate.
Claim 6
Dependent Claim
60 words
A method according to claim 2 , in which at least one of said collectors is disposed over said insulating buried layer and bounded by shallow isolation trenches, thereby forming an epitaxial collector block and in which said insulating layer surrounds said epitaxial collector block, whereby said epitaxial collector block is encapsulated in insulator and isolated from said silicon substrate.
Claim 7
Dependent Claim
153 words
A method according to claim 2 , in which said steps of depositing an insulating layer above said device layer in said CMOS region and said step of planarizing said insulating layer so that said epitaxial layer top surface and said insulating layer top surface are substantially coplanar are replaced by: a step of depositing a first insulating layer above at least said CMOS region and planarizing said first insulating layer to a first insulating layer top surface coplanar with a gate top surface of said CMOS transistor gates; depositing a first conductive layer above said first insulating layer top surface and patterning said first conductive layer to form a first interconnect layer connecting at least some of said CMOS transistors; and depositing a second insulating layer above said interconnect layer and planarizing said second insulating layer so that said epitaxial layer top surface and said insulating layer top surface are substantially coplanar.
Claim 8
Dependent Claim
50 words
A method according to claim 2 , further including a step of forming said buried insulating layer in said CMOS region and in a subregion of said bipolar region, whereby at least some of said bipolar region is disposed over said silicon substrate and not over said buried insulating layer.
Claim 9
Dependent Claim
40 words
A method according to claim 1 , in which silicon contact areas of said CMOS transistors and said bipolar transistors are exposed, a layer of metal is deposited and heated to form self-aligned silicide with said exposed silicon contact areas.
Claim 10
Dependent Claim
60 words
A method according to claim 8 , in which at least one of said collectors is disposed over said insulating buried layer and bounded by shallow isolation trenches, thereby forming an epitaxial collector block and in which said insulating layer surrounds said epitaxial collector block, whereby said epitaxial collector block is encapsulated in insulator and isolated from said silicon substrate.
Claim 11
Dependent Claim
153 words
A method according to claim 8 , in which said steps of depositing an insulating layer above said device layer in said CMOS region and said step of planarizing said insulating layer so that said epitaxial layer top surface and said insulating layer top surface are substantially coplanar are replaced by: a step of depositing a first insulating layer above at least said CMOS region and planarizing said first insulating layer to a first insulating layer top surface coplanar with a gate top surface of said CMOS transistor gates; depositing a first conductive layer above said first insulating layer top surface and patterning said first conductive layer to form a first interconnect layer connecting at least some of said CMOS transistors; and depositing a second insulating layer above said interconnect layer and planarizing said second insulating layer so that said epitaxial layer top surface and said insulating layer top surface are substantially coplanar.
Claim 12
Dependent Claim
50 words
A method according to claim 8 , further including a step of forming said buried insulating layer in said CMOS region and in a subregion of said bipolar region, whereby at least some of said bipolar region is disposed over said silicon substrate and not over said buried insulating layer.
Claim 13
Dependent Claim
60 words
A method according to claim 1 , in which at least one of said collectors is disposed over said insulating buried layer and bounded by shallow isolation trenches, thereby forming an epitaxial collector block and in which said insulating layer surrounds said epitaxial collector block, whereby said epitaxial collector block is encapsulated in insulator and isolated from said silicon substrate.
Claim 14
Dependent Claim
153 words
A method according to claim 12 , in which said steps of depositing an insulating layer above said device layer in said CMOS region and said step of planarizing said insulating layer so that said epitaxial layer top surface and said insulating layer top surface are substantially coplanar are replaced by: a step of depositing a first insulating layer above at least said CMOS region and planarizing said first insulating layer to a first insulating layer top surface coplanar with a gate top surface of said CMOS transistor gates; depositing a first conductive layer above said first insulating layer top surface and patterning said first conductive layer to form a first interconnect layer connecting at least some of said CMOS transistors; and depositing a second insulating layer above said interconnect layer and planarizing said second insulating layer so that said epitaxial layer top surface and said insulating layer top surface are substantially coplanar.
Claim 15
Dependent Claim
50 words
A method according to claim 12 , further including a step of forming said buried insulating layer in said CMOS region and in a subregion of said bipolar region, whereby at least some of said bipolar region is disposed over said silicon substrate and not over said buried insulating layer.
Claim 16
Dependent Claim
152 words
A method according to claim 1 , in which said steps of depositing an insulating layer above said device layer in said CMOS region and said step of planarizing said insulating layer so that said epitaxial layer top surface and said insulating layer top surface are substantially coplanar are replaced by: a step of depositing a first insulating layer above at least said CMOS region and planarizing said first insulating layer to a first insulating layer top surface coplanar with a gate top surface of said CMOS transistor gates; depositing a first conductive layer above said first insulating layer top surface and patterning said first conductive layer to form a-first interconnect layer connecting at least some of said CMOS transistors; and depositing a second insulating layer above said interconnect layer and planarizing said second insulating layer so that said epitaxial layer top surface and said insulating layer top surface are substantially coplanar.
Claim 17
Dependent Claim
50 words
A method according to claim 1 , further including a step of forming said buried insulating layer in said CMOS region and in a subregion of said bipolar region, whereby at least some of said bipolar region is disposed over said silicon substrate and not over said buried insulating layer.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-05-21 | 2004-11-20 | 2005-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-05-21 | 2008-11-20 | 2009-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-05-21 | 2012-11-20 | 2013-05-22 | $7700.00 | Window Closed / Lapsed |