US6235557B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Programmable fuse and method therefor
Assignee: NXP BV
•
Filing: 1999-04-28
•
Granted: 2001-05-22
•
Expires: 2019-04-28
Abstract
Abstract A programmable fuse implements redundancy in semiconductor devices and enables the repair of defective elements. In an example embodiment, a fuse is built in the second-to-the-last metal interconnect layer used in the circuit. An opening to expose the fuse is incorporated into an existing mask of the last metal interconnect layer, typically the pad mask. The passivation layer on top of the bond pads is opened to expose the bonding pads. At the same time, a residual oxide window is defined over the fuse. The residual oxide covering the fuse provides for a reliable and reproducible fuse.
Inventors
- 👤 Martin Manley
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:52
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/493; H10W20/494
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
162 words
A method of forming a fuse in a second-to-the-last metal interconnect layer, the second-to-the-last metal interconnect layer of a semiconductor device substrate having at least two metal interconnect layers comprising: forming the fuse in the second-to-the-last metal interconnect layer; forming a first oxide layer over the fuse; depositing a last metal interconnect layer on the first oxide layer and forming a bonding pad therefrom; forming a second oxide layer over the bonding pad and the first oxide layer; forming a nitride layer over the second oxide layer; masking the nitride layer to define a first region over the fuse and a second region over the bonding pad; and etching the nitride layer in the first and second region with a first etchant until the nitride layer is removed to form apertures in the first and second region, changing to a second etchant and resuming etching in the second oxide layer in the first and second region until the bonding pad is exposed.
Claim 2
Independent Claim
162 words
A method of forming a fuse in a second-to-the-last metal interconnect layer, the second-to-the-last metal interconnect layer of a semiconductor device substrate having at least two metal interconnect layers comprising: forming the fuse in the second-to-the-last metal interconnect layer; forming a first oxide layer over the fuse; depositing a last metal interconnect layer on the first oxide layer and forming a bonding pad therefrom; forming a second oxide layer over the bonding pad and the first oxide layer; forming a nitride layer over the second oxide layer; masking the nitride layer to define a first region over the fuse and a second region over the bonding pad; and etching the nitride layer in the first and second region with a first etchant until the nitride layer is removed to form apertures in the first and second region, changing to a second etchant and resuming etching in the second oxide layer in the first and second region until the bonding pad is exposed.
Claim 3
Dependent Claim
46 words
The method of forming a fuse as recited in claim 1 wherein in an N metal layer process, the second-to-the-last metal layer is an (N−1) th metal layer and the last metal layer an N th metal layer wherein N is an integer greater than two.
Claim 4
Dependent Claim
37 words
The method of forming a fuse as recited in claim 1 wherein in a five metal layer process, the second-to-the-last metal layer is a fourth metal layer and the last metal layer is a fifth metal layer.
Claim 5
Dependent Claim
37 words
The method of forming a fuse as recited in claim 1 wherein in a four metal layer process, the second-to-the-last metal layer is a third metal layer and the last metal layer is a fourth metal layer.
Claim 6
Dependent Claim
36 words
The method of forming a fuse as recited in claim 1 wherein in a three metal layer process, the second-to-the-last metal layer is a second metal layer and the last metal layer is a third layer.
Claim 7
Dependent Claim
34 words
The method of claim 1 wherein the second-to-last and the last metal interconnect layers includes using alloys selected from at least one of the following: aluminum, copper, titanium, tungsten, platinum, molybdenum, cobalt, and tantalum.
Claim 8
Independent Claim
226 words
A method of manufacturing a semiconductor device having a second-to-the-last metal interconnect layer, the second-to-the-last metal interconnect layer on an insulating layer of a semiconductor device substrate having at least two metal interconnect layers comprising: forming fuses in the second-to-the-last metal interconnect layer; forming a first oxide layer over the fuses and the insulating layer; depositing a last metal interconnect layer on the first oxide layer and forming at least one bonding pad therefrom; forming a second oxide layer over the plurality of the bonding pad and the first oxide layer; forming a nitride layer over the second oxide layer; masking the nitride layer to define a first region over the fuse and a second region over the bonding pad; etching the nitride layer in the first and second region with a first etchant until the nitride layer is removed to form apertures in the first and second region, changing to a second etchant and resuming etching in the second oxide layer in the first and second region until the bonding pad is exposed; and putting a first group of the fuses into a first state and a second group of the fuses different from the first group of fuses into a second state, the electrical resistance of the first group of the fuses being much greater than that of the fuses in the second state.
Claim 9
Independent Claim
226 words
A method of manufacturing a semiconductor device having a second-to-the-last metal interconnect layer, the second-to-the-last metal interconnect layer on an insulating layer of a semiconductor device substrate having at least two metal interconnect layers comprising: forming fuses in the second-to-the-last metal interconnect layer; forming a first oxide layer over the fuses and the insulating layer; depositing a last metal interconnect layer on the first oxide layer and forming at least one bonding pad therefrom; forming a second oxide layer over the plurality of the bonding pad and the first oxide layer; forming a nitride layer over the second oxide layer; masking the nitride layer to define a first region over the fuse and a second region over the bonding pad; etching the nitride layer in the first and second region with a first etchant until the nitride layer is removed to form apertures in the first and second region, changing to a second etchant and resuming etching in the second oxide layer in the first and second region until the bonding pad is exposed; and putting a first group of the fuses into a first state and a second group of the fuses different from the first group of fuses into a second state, the electrical resistance of the first group of the fuses being much greater than that of the fuses in the second state.
Claim 10
Dependent Claim
47 words
The method of manufacturing a semiconductor device as recited in claim 7 wherein in an N metal layer process, the second-to-the-last metal layer is an (N−1) th metal layer and the last metal layer is an N th layer, wherein N is an integer greater than two.
Claim 11
Dependent Claim
34 words
The method of claim 7 wherein the second-to-last and the last metal interconnect layers includes using alloys selected from at least one of the following: aluminum, copper, titanium, tungsten, platinum, molybdenum, cobalt, and tantalum.
Claim 12
Dependent Claim
35 words
The method of manufacturing a semiconductor device as recited in claim 7 wherein putting the first group of fuses into the first state comprises using a laser beam to open the first group of fuses.
Claim 13
Dependent Claim
35 words
The method of manufacturing a semiconductor device as recited in claim 7 wherein putting the first group of fuses into the first state comprises using an electrical current to open the first group of fuses.
Claim 14
Independent Claim
227 words
A method of manufacturing a semiconductor device having a second-to-the-last metal interconnect layer, the second-to-the-last metal interconnect layer on a substrate insulating layer of a semiconductor device substrate having at least two metal interconnect layers comprising: forming fuses in the second-to-the-last metal interconnect layer; forming a first dielectric layer over the fuses and the substrate insulating layer; depositing a last metal interconnect layer on the first dielectric layer and forming at least one bonding pad therefrom; forming a second dielectric layer over the bonding pad and the first dielectric layer; forming a third dielectric layer over the second dielectric layer; masking the third layer to define a first region over the fuse and a second region over the bonding pad; etching the third dielectric layer in the first and second region with a first etchant until the nitride layer is removed to form apertures in the first and second region, changing to a second etchant and resuming etching in the second dielectric layer in the first and second region until the bonding pad is exposed; and putting a first group of the fuses into a first state and a second group of the fuses different from the first group of fuses into a second state, the electrical resistance of the first group of the fuses being much greater than that of the fuses in the second state.
Claim 15
Independent Claim
227 words
A method of manufacturing a semiconductor device having a second-to-the-last metal interconnect layer, the second-to-the-last metal interconnect layer on a substrate insulating layer of a semiconductor device substrate having at least two metal interconnect layers comprising: forming fuses in the second-to-the-last metal interconnect layer; forming a first dielectric layer over the fuses and the substrate insulating layer; depositing a last metal interconnect layer on the first dielectric layer and forming at least one bonding pad therefrom; forming a second dielectric layer over the bonding pad and the first dielectric layer; forming a third dielectric layer over the second dielectric layer; masking the third layer to define a first region over the fuse and a second region over the bonding pad; etching the third dielectric layer in the first and second region with a first etchant until the nitride layer is removed to form apertures in the first and second region, changing to a second etchant and resuming etching in the second dielectric layer in the first and second region until the bonding pad is exposed; and putting a first group of the fuses into a first state and a second group of the fuses different from the first group of fuses into a second state, the electrical resistance of the first group of the fuses being much greater than that of the fuses in the second state.
Claim 16
Dependent Claim
38 words
The method of forming a fuse as recited in claim 12 wherein in an N metal layer process, the second-to-the-last metal layer is an (N−1) th metal layer and the last metal layer is an N th layer.
Claim 17
Dependent Claim
32 words
The method of claim 12 wherein the second-to-last and the last metal interconnect layers includes using alloys selected from the group consisting of: aluminum, copper, titanium, tungsten, platinum, molybdenum, cobalt and tantalum.
Claim 18
Dependent Claim
37 words
The method of claim 12 wherein the first dielectric layer, the second dielectric layer, and the third dielectric layer are selected from the group consisting of: silicon dioxide, silicon oxynitride, silicon nitride, silicon oxyfluoride and phospho-silicate glass.
Claim 19
Dependent Claim
35 words
The method of manufacturing a semiconductor device as recited in claim 12 wherein putting the first group of fuses into the first state comprises using a laser beam to open the first group of fuses.
Claim 20
Dependent Claim
35 words
The method of manufacturing a semiconductor device as recited in claim 12 wherein putting the first group of fuses into the first state comprises using an electrical current to open the first group of fuses.
Claim 21
Independent Claim
124 words
A method of forming an integrated circuit having memory redundancy comprising: forming a semiconductor array of memory cells arranged in rows and columns, with each memory cell to be accessed in response to levels established on selected ones of row and bit lines, forming a fuse-link circuit coupled to certain ones of the row and bit lines, wherein the forming of the fuse-link comprises: forming a fuse having an insulated portion and an exposed portion; covering the exposed portion with a first insulator; forming a second insulator over the first insulator; and selectively removing the second insulator and exposing the first insulator via an aperture above the fuse layer, and repairing at least one defective memory cell in the array by opening the fuse-link.
Claim 22
Independent Claim
124 words
A method of forming an integrated circuit having memory redundancy comprising: forming a semiconductor array of memory cells arranged in rows and columns, with each memory cell to be accessed in response to levels established on selected ones of row and bit lines, forming a fuse-link circuit coupled to certain ones of the row and bit lines, wherein the forming of the fuse-link comprises: forming a fuse having an insulated portion and an exposed portion; covering the exposed portion with a first insulator; forming a second insulator over the first insulator; and selectively removing the second insulator and exposing the first insulator via an aperture above the fuse layer, and repairing at least one defective memory cell in the array by opening the fuse-link.
Claim 23
Dependent Claim
145 words
The method as recited in claim 18 wherein forming a fuse further comprises: forming the fuse in a second-to-the-last metal interconnect layer; forming a first oxide layer over the fuse; depositing a last metal interconnect layer on the first oxide layer and forming a bonding pad therefrom; forming a second oxide layer over the bonding pad and the first oxide layer; forming a nitride layer over the second oxide layer; masking the nitride layer to define a first region over the fuse and a second region over the bonding pad; and etching the nitride layer in the first and second region with a first etchant until the nitride layer is removed to form apertures in the first and second region, changing to a second etchant and resuming etching in the second oxide layer in the first and second region until the bonding pad is exposed.
Claim 24
Dependent Claim
44 words
The method of forming a fuse as recited in claim 19 wherein in an N-metal layer process, the second-to-the-last metal is an (N−1) th metal layer and the last metal layer an N th metal layer wherein N is an integer greater than two.
References Cited (Backward Citations)
US4413272A
Cited
US4455194A
Cited
US4536949A
Cited
US4628590A
Cited
US5444012A
Cited
US5550399A
Cited
US5844295A
Cited
US5972756A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-05-21 | 2004-11-20 | 2005-05-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-05-21 | 2008-11-20 | 2009-05-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-05-21 | 2012-11-20 | 2013-05-22 | $7700.00 | Window Closed / Lapsed |