US5444012A
Expired / Lapsed
US
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Method for manufacturing semiconductor integrated circuit device having a fuse element
Assignee: Hitachi Ltd
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Filing: 1994-07-20
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Granted: 1995-08-22
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Expires: 2014-07-20
Abstract
Abstract In depositing a silicon oxide film which constitutes part of a final passivation film onto a bonding pad formed on an interlayer insulating film, the silicon oxide depositing step is divided in two stages, and after the first deposition, the bonding pad is once exposed by etching, then the second deposition is performed, whereby the silicon oxide film which has thus been deposited in two stages is formed over a fuse element formed under the interlayer insulating film, while on the bonding pad is formed only the silicon oxide film deposited in the second stage. As a result, at the time of etching polyimide resin, silicon nitride film and silicon oxide film successively to expose the bonding pad, there remains a sufficient thickness of insulating film between the bottom of an aperture which is formed at the same time and the fuse element. Thereafter, an electrical test is conducted while applying a probe to the bonding pad and, where required, the fuse element located under the aperture is cut.
Inventors
- 👤 Keiichi Yoshizumi
- 👤 Kazushi Fukuda
- 👤 Seiichi Ariga
- 👤 Shuji Ikeda
- 👤 Makoto Saeki
- 👤 Kiyoshi Nagai
- 👤 Soichiro Hashiba
- 👤 Shinji Nishihara
- 👤 Fumiyuki Kanai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:49
CPC Classifications
H; H10; H10B; H10B10/00; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/493; Y; Y10; Y10S; Y10S148/00; Y10S148/055
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
203 words
A method for manufacturing a semiconductor integrated circuit device, comprising steps of: (a) providing a semiconductor substrate having a main surface, with a fuse element on said main surface; (b) forming an interlayer insulating film over said fuse element so as to cover said fuse element and said main surface; (c) forming a wiring line having a bonding pad forming region on said interlayer insulating film; (d) forming a first insulating film on said wiring line and said interlayer insulating film so as to cover said main surface; (e) selectively removing said first insulating film on said bonding pad forming region by etching; (f) forming a second insulating film on said bonding pad forming region and said first insulating film so as to cover said main surface; (g) selectively removing said second insulating film on said bonding pad forming region and said fuse element so as to expose said bonding pad forming region of said wiring line and so as to form an aperture over said fuse element by etching; (h) conducting an electrical test while applying a probe to said bonding pad forming region; and (i) cutting the fuse element under said aperture in accordance with the results of said electrical test.
Claim 2
Independent Claim
203 words
A method for manufacturing a semiconductor integrated circuit device, comprising steps of: (a) providing a semiconductor substrate having a main surface, with a fuse element on said main surface; (b) forming an interlayer insulating film over said fuse element so as to cover said fuse element and said main surface; (c) forming a wiring line having a bonding pad forming region on said interlayer insulating film; (d) forming a first insulating film on said wiring line and said interlayer insulating film so as to cover said main surface; (e) selectively removing said first insulating film on said bonding pad forming region by etching; (f) forming a second insulating film on said bonding pad forming region and said first insulating film so as to cover said main surface; (g) selectively removing said second insulating film on said bonding pad forming region and said fuse element so as to expose said bonding pad forming region of said wiring line and so as to form an aperture over said fuse element by etching; (h) conducting an electrical test while applying a probe to said bonding pad forming region; and (i) cutting the fuse element under said aperture in accordance with the results of said electrical test.
Claim 3
Dependent Claim
60 words
A method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein, in said step (c), said wiring line comprises at least a metallic film and an anti-reflection film formed on said metallic film, and wherein, in said step (e), the anti-reflection film and the first insulating film on said bonding pad forming region are removed by etching.
Claim 4
Dependent Claim
82 words
A method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein said semiconductor integrated circuit device has a SRAM including a memory cell, said memory cell comprising a MISFET for transfer controlled by a word line and a flip-flop circuit which comprises a MISFET for drive and a MISFET for load, said MISFET for load being constituted by a polysilicon film deposited on said MISFET for drive, and said interlayer insulating film is formed on said MISFET for load.
Claim 5
Dependent Claim
35 words
A method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein after said step (i) there is conducted a second electrical test while applying the probe to said bonding pad forming region.
Claim 6
Dependent Claim
72 words
A method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein said first insulating film and said second insulating film are each a silicon oxide film, and said interlayer insulating film is a BPSG film, and wherein said fuse element is formed by a polysilicon film simultaneously with formation of a gate electrode of said MISFET for transfer in the same step as that of forming said gate electrode.
Claim 7
Dependent Claim
81 words
A method for manufacturing a semiconductor integrated circuit device according to claim 3, further comprising, between said steps (b) and (c), steps of: (j) forming an opening in said interlayer insulating film and around said fuse element; and (k) providing a guard ring over said opening and said interlayer insulating film, said guard ring being formed by the same layer of wiring line as said wiring line, wherein said guard ring is formed around said aperture formed in said step (g).
Claim 8
Dependent Claim
79 words
A method for manufacturing a semiconductor integrated circuit device according to claim 2, wherein said semiconductor integrated circuit device has a SRAM including a memory cell, said memory cell comprising a MISFET for transfer controlled by a word line and a flip-flop circuit which comprises a MISFET for drive and a load resistor, said load resistor being constituted by a polysilicon film deposited on said MISFET for drive, and said interlayer insulating film is formed on said load resistor.
Claim 9
Dependent Claim
23 words
A method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein said anti-reflection film is formed of TiN or TiW.
Claim 10
Independent Claim
246 words
A method for manufacturing a semiconductor integrated circuit device which method, in forming a bonding pad on an interlayer insulating film which covers a fuse element, etching a final passivation film deposited on said bonding pad to expose the bonding pad and forming an aperture over said fuse element, comprises the steps of: (a) forming a wiring line integrally with said bonding pad on said interlayer insulating film which covers said fuse element; (b) depositing a silicon oxide film which constitutes part of said final passivation film over the whole surface of said interlayer insulating film; (c) etching said silicon oxide film on said bonding pad to expose the bonding pad, and thereafter depositing again the silicon oxide film which constitutes part of said final passivation film over the whole surface of the silicon oxide film deposited initially; (d) depositing a silicon nitride film which constitutes part of said final passivation film over the whole surface of said silicon oxide film; (e) etching said silicon nitride film on said bonding pad to expose said silicon oxide film; (f) depositing a polyimide resin over the whole surface of said silicon nitride film; (g) etching successively said polyimide resin and said silicon oxide on said bonding pad and said fuse element to expose the bonding pad and form an aperture over the fuse element; (h) conducting an electrical test while applying a probe to said bonding pad and, where required, cutting said fuse element located under said aperture.
Claim 11
Independent Claim
246 words
A method for manufacturing a semiconductor integrated circuit device which method, in forming a bonding pad on an interlayer insulating film which covers a fuse element, etching a final passivation film deposited on said bonding pad to expose the bonding pad and forming an aperture over said fuse element, comprises the steps of: (a) forming a wiring line integrally with said bonding pad on said interlayer insulating film which covers said fuse element; (b) depositing a silicon oxide film which constitutes part of said final passivation film over the whole surface of said interlayer insulating film; (c) etching said silicon oxide film on said bonding pad to expose the bonding pad, and thereafter depositing again the silicon oxide film which constitutes part of said final passivation film over the whole surface of the silicon oxide film deposited initially; (d) depositing a silicon nitride film which constitutes part of said final passivation film over the whole surface of said silicon oxide film; (e) etching said silicon nitride film on said bonding pad to expose said silicon oxide film; (f) depositing a polyimide resin over the whole surface of said silicon nitride film; (g) etching successively said polyimide resin and said silicon oxide on said bonding pad and said fuse element to expose the bonding pad and form an aperture over the fuse element; (h) conducting an electrical test while applying a probe to said bonding pad and, where required, cutting said fuse element located under said aperture.
Claim 12
Dependent Claim
202 words
A method for manufacturing a semiconductor integrated circuit device according to claim 9, wherein, in said step (a), said wiring line comprises at least a metallic film and an anti-reflection film formed on said metallic film, wherein by said etching in said step (c) the anti-reflection film and the silicon oxide film are removed and said bonding pad is exposed thereby, wherein said anti-reflection film is formed of TiN or TiW, wherein said semiconductor integrated circuit device has a SRAM including a memory cell, said memory cell comprising a MISFET for transfer controlled by a word line and a flip-flop circuit which comprises a MISFET for drive and a MISFET for load, said MISFET for load being constituted by a polysilicon film deposited on said MISFET for drive, wherein said interlayer insulating film includes a BPSG film, and said silicon oxide film is formed on said BPSG film, wherein after said step (h) there is conducted a second electrical test while applying the probe to said bonding pad, and wherein said fuse element is formed by a polysilicon film simultaneously with formation of a gate electrode of said MISFET for transfer in the same step as that of forming said gate electrode.
Claim 13
Dependent Claim
24 words
A method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein hydrogen annealing is performed between said steps (c) and (d).
Claim 14
Dependent Claim
39 words
A method for manufacturing a semiconductor integrated circuit device according to claim 10, wherein a guard ring formed by the same layer of wiring line as said wiring line is disposed around said aperture formed over said fuse element.
References Cited (Backward Citations)
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| 3.5 Years (Year 4) | 1998-08-21 | 1999-02-20 | 1999-08-22 | $2000.00 | Window Closed / Lapsed |
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