Patent US6232796B1 successfully refreshed from Google Patents.
US6232796B1
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US
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Apparatus and method for detecting two data bits per clock edge
Assignee: Rambus Inc
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Filing: 1999-07-21
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Granted: 2001-05-15
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Expires: 2019-07-21
Abstract
Abstract A method of detecting two bits of data transmitted with a single clock edge includes the step of assessing the value of a first data bit and a second data bit transmitted with a single clock edge to generate a first output bit indicative of the value of said first data bit. The assessing step may be implemented by integrating the first data bit and the second data bit, or by identifying signal transitions between the first data bit and the second data bit. The second output bit is produced by simply passing the second data bit.
Inventors
- 👤 Pradeep Batra
- 👤 Stefanos Sidiropoulos
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 08:55
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1078; G11C7/1084; G11C7/1087; H; H03; H03K; H03K5/00; H03K5/01; H03K5/08; H03K5/13; H03K5/135; G11C2207/00; G11C2207/10; G11C2207/107
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
120 words
A circuit for detecting two bits of data transmitted with a single clock edge, said circuit comprising: a first circuit module to assess a combined value of a first data bit and a second data bit sequentially transmitted with a single clock edge and generate a first output bit indicative of a value of said first data bit; said first circuit module including an integrator to integrate said first data bit and said second data bit to generate an analog output value, and a plurality of comparators to convert said analog output value to a plurality of digital output values; and a second circuit module to pass a value of said second data bit to produce a second output bit.
Claim 2
Dependent Claim
120 words
A circuit for detecting two bits of data transmitted with a single clock edge, said circuit comprising: a first circuit module to assess a combined value of a first data bit and a second data bit sequentially transmitted with a single clock edge and generate a first output bit indicative of a value of said first data bit; said first circuit module including an integrator to integrate said first data bit and said second data bit to generate an analog output value, and a plurality of comparators to convert said analog output value to a plurality of digital output values; and a second circuit module to pass a value of said second data bit to produce a second output bit.
Claim 3
Dependent Claim
31 words
The circuit of claim 1 wherein said first circuit module further includes combinatorial logic to process said digital output value and said second output bit to produce said first output bit.
Claim 4
Dependent Claim
19 words
The circuit of claim 2 wherein said combinatorial logic includes a logical AND gate and a logical OR gate.
Claim 5
Dependent Claim
35 words
The circuit of claim 1 wherein said second circuit module includes a transmission gate controlled by said single clock edge, said transmission gate selectively passing said second data bit to produce said second output bit.
Claim 6
Dependent Claim
118 words
A circuit for detecting two bits of data transmitted with a single clock edge, said circuit comprising: a first level-sensitive latch to identify a high-to-low transition between a first data bit and a second data bit transmitted with a single clock edge; and a second level-sensitive latch to identify a low-to-high transition between said first data bit and said second data bit, said first level-sensitive latch and said second level-sensitive latch producing a signal transition digital signal; a circuit module to pass a value of said second data bit to produce a second output bit; and combinatorial logic to process said signal transition digital signal and said second output bit data bit to produce a first output bit.
Claim 7
Dependent Claim
118 words
A circuit for detecting two bits of data transmitted with a single clock edge, said circuit comprising: a first level-sensitive latch to identify a high-to-low transition between a first data bit and a second data bit transmitted with a single clock edge; and a second level-sensitive latch to identify a low-to-high transition between said first data bit and said second data bit, said first level-sensitive latch and said second level-sensitive latch producing a signal transition digital signal; a circuit module to pass a value of said second data bit to produce a second output bit; and combinatorial logic to process said signal transition digital signal and said second output bit data bit to produce a first output bit.
Claim 8
Dependent Claim
29 words
The circuit of claim 5 wherein said combinatorial logic includes an exclusive-OR gate and an OR gate to process said signal transition digital signal and said second data bit.
Claim 9
Dependent Claim
35 words
The circuit of claim 5 wherein said second circuit module includes a transmission gate controlled by said single clock edge, said transmission gate selectively passing said second data bit to produce said second output bit.
Claim 10
Dependent Claim
23 words
The circuit of claim 7 wherein said second circuit module further includes a flip-flop connected to the output node of said transmission gate.
Claim 11
Independent Claim
101 words
A method of detecting two bits of data transmitted with a single clock edge, said method comprising: assessing a first data bit and a second data bit sequentially transmitted with a single clock edge, including integrating said first data bit and said second data bit to generate an analog output value, and converting said analog output value to a plurality of digital outout values; generating a first output bit indicative of a value of said first data bit based on said plurality of digital output values; and passing a value of said second data bit to produce a second output bit.
Claim 12
Independent Claim
101 words
A method of detecting two bits of data transmitted with a single clock edge, said method comprising: assessing a first data bit and a second data bit sequentially transmitted with a single clock edge, including integrating said first data bit and said second data bit to generate an analog output value, and converting said analog output value to a plurality of digital outout values; generating a first output bit indicative of a value of said first data bit based on said plurality of digital output values; and passing a value of said second data bit to produce a second output bit.
Claim 13
Dependent Claim
31 words
The method of claim 9 wherein said assessing further includes processing said plurality of digital output values and said second output bit with combinatorial logic to produce said first output bit.
Claim 14
Dependent Claim
30 words
The method of claim 9 wherein said passing includes routing said second data bit through a transmission gate controlled by said single clock edge to produce said second output bit.
Claim 15
Independent Claim
98 words
A method of detecting two bits of data transmitted with a single clock edge, said method comprising: assessing a first data bit and a second data bit sequentially transmitted with a single clock edge, including generating a signal transition digital signal in response to a signal transition between said first data bit and said second data bit; passing a value of said second data bit to produce a second output bit; and generating a first output bit indicative of a value of said first data bit based on said signal transition digital signal and said second output bit.
Claim 16
Independent Claim
98 words
A method of detecting two bits of data transmitted with a single clock edge, said method comprising: assessing a first data bit and a second data bit sequentially transmitted with a single clock edge, including generating a signal transition digital signal in response to a signal transition between said first data bit and said second data bit; passing a value of said second data bit to produce a second output bit; and generating a first output bit indicative of a value of said first data bit based on said signal transition digital signal and said second output bit.
Claim 17
Dependent Claim
29 words
The method of claim 12 wherein said assessing includes processing said signal transition digital signal and said second data bit with combinatorial logic to produce said first output bit.
Claim 18
Dependent Claim
34 words
The method of claim 11 wherein said passing includes routing said second data bit through a transmission gate controlled by said single clock edge and through a flip-flop to produce said second output bit.
Claim 19
Dependent Claim
102 words
A circuit for detecting a first data bit and a second data bit sequentially transmitted on a single transmission line with a single clock edge, said circuit comprising: a first circuit module to pass a value of said second data bit to produce a first output representing the value of said second data bit; and a second circuit module comprising first circuitry to generate a first signal when said first data bit and second data bit differ and second circuitry to generate a second output representing a value of said first data bit based on said first signal and said first output.
Claim 20
Dependent Claim
102 words
A circuit for detecting a first data bit and a second data bit sequentially transmitted on a single transmission line with a single clock edge, said circuit comprising: a first circuit module to pass a value of said second data bit to produce a first output representing the value of said second data bit; and a second circuit module comprising first circuitry to generate a first signal when said first data bit and second data bit differ and second circuitry to generate a second output representing a value of said first data bit based on said first signal and said first output.
Claim 21
Dependent Claim
14 words
The circuit of claim 15 wherein said first circuit module comprises a transmission gate.
Claim 22
Dependent Claim
28 words
The circuit of claim 16 wherein said second circuitry comprises an integrator to integrate said first data bit and said second data bit and generate an integrated output.
Claim 23
Dependent Claim
67 words
The circuit of claim 17 wherein said second circuitry includes: a first comparator to generate said first signal based on said integrated output and a first reference signal; a second comparator to generate a second signal based on said integrated output and a second reference signal; and combinatorial logic circuitry to receive said first output, said first signal and said second signal, and generate said second output.
Claim 24
Dependent Claim
60 words
The circuit of claim 15 wherein said second circuitry further comprises: a first level-sensitive latch to detect a low-to-high transition and produce said first signal; a second level-sensitive latch to detect a high-to-low transition and produce a second signal; and combinatorial logic circuitry to receive said first output, said first signal and said second signal, and generate said second output.
Claim 25
Dependent Claim
81 words
A data communication method using a clock signal having a first phase and a second phase, said method comprising: receiving in sequence a first bit and a second bit during said first phase; generating a first signal when said first bit and said second bit differ; generating a first output representing a value of said second bit; and generating a second output representing a value of said first bit based on said first signal and said value of said second bit.
Claim 26
Dependent Claim
81 words
A data communication method using a clock signal having a first phase and a second phase, said method comprising: receiving in sequence a first bit and a second bit during said first phase; generating a first signal when said first bit and said second bit differ; generating a first output representing a value of said second bit; and generating a second output representing a value of said first bit based on said first signal and said value of said second bit.
Claim 27
Dependent Claim
17 words
The method of claim 20 wherein said second bit is received after said first bit is received.
Claim 28
Dependent Claim
39 words
The method of claim 21 wherein said generating said first signal comprises: integrating said first bit and said second bit to produce an integrated output; and comparing said integrated output with a reference signal to generate said first signal.
Claim 29
Dependent Claim
22 words
The method of claim 22 further comprising: generating a second signal when said first bit and said second bit are logic high.
Claim 30
Dependent Claim
59 words
The method of claim 21 wherein said first signal is generated when said second bit is logic high; and generating said second output includes: generating a second signal when said first bit is logic high and said second bit is logic low; and generating said second output based on said first signal, said second signal and said first output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-05-14 | 2004-11-13 | 2005-05-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-05-14 | 2008-11-13 | 2009-05-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-05-14 | 2012-11-13 | 2013-05-15 | $7700.00 | Window Closed / Lapsed |