MOS transistors having raised source and drain and interconnects

Claim 2

A process of fabricating on a substrate a semiconductor device having a gate electrode, a raised source, a raised drain and an interconnect, comprising the steps of: forming sequentially a first dielectric layer and a first conductor layer on said substrate; forming one or more inset isolation regions in said substrate by removing portions of said first conductor layer, said first dielectric layer and said substrate underlying said first dielectric layer; filling each said inset isolation region with an isolation layer; forming a second dielectric layer on top of said first conductor layer and said isolation layers; simultaneously forming a first trench by removing a portion of each of said second dielectric layer, said first conductor layer, said first dielectric layer and said substrate underlying said first dielectric layer and forming a second trench by removing a portion of said isolation layer; forming a plurality of cavities at the bottom of said first trench by laterally removing portions of said first dielectric layer; filling each said cavity with a second conductor layer; forming a plurality of dielectric sidewalls and a dielectric bottom layer in said first trench; forming said gate electrode and said interconnect by filling said first trench and said second trench with a third conductor layer; doping said first conductor layer with dopants; and forming said raised source and said raised drain by driving said dopants into said substrate.

Claim 3

The process of claim 1 , further comprising the step of forming a lightly doped well in said substrate between said step of filling the inset isolation regions and said step of forming the second dielectric layer.

Claim 4

The process of claim 2 , wherein said isolation layers are silicon dioxide layers.

Claim 5

The process of claim 3 , wherein said step of filling said inset isolation region comprises two consecutive steps of: depositing said isolation layer on said substrate; and removing said isolation layer other than the portions filling said inset isolation region.

Claim 6

The process of claim 2 , wherein said step of forming said inset isolation regions is carried out by anisotropic etching.

Claim 7

The process of claim 5 , wherein said step of forming said first trench and said second trench is carried out by anisotropic etching.

Claim 8

The process of claim 6 , wherein said step of forming said cavities in said first trench is carried out by isotropic etching.

Claim 9

The process of claim 7 , wherein said step of filling said cavities comprises two consecutive steps of: depositing said second conductor layer on said substrate; and removing said second conductor layer other than the portions filling said cavities.

Claim 10

The process of claim 8 , wherein the material for said second conductor layer is selected from the group consisting of CVD poly-Si, CVD metals, metal silicides, CVD epi-Si, selective-growth epi-Si and selective-growth W.

Claim 11

The process of claim 8 , wherein said step of forming said raised source and said raised drain is carried out by annealing.

Claim 12

A semiconductor device having a gate electrode, a raised source, a raised drain and an interconnect, fabricated on a substrate by a process comprising the steps of: forming sequentially a first dielectric layer and a first conductor layer on said substrate; forming one or more inset isolation regions in said substrate by removing portions of said first conductor layer, said first dielectric layer and said substrate underlying said first dielectric layer; filling each said inset isolation region with an isolation layer; forming a second dielectric layer on top of said first conductor layer and said isolation layers; simultaneously forming a first trench by removing a portion of each of said second dielectric layer, said first conductor layer, said first dielectric layer and said substrate underlying said first dielectric layer and forming a second trench by removing a portion of said isolation layer; forming a plurality of cavities at the bottom of said first trench by laterally removing portions of said first dielectric layer; filling each said cavity with a second conductor layer; forming a plurality of dielectric sidewalls and a dielectric bottom layer in said first trench; forming said gate electrode and said interconnect by filling said first trench and said second trench with a third conductor layer; doping said first conductor layer with dopants; and forming said raised source and said raised drain by driving said dopants into the surface region of said substrate.

Claim 13

A semiconductor device having a gate electrode, a raised source, a raised drain and an interconnect, fabricated on a substrate by a process comprising the steps of: forming sequentially a first dielectric layer and a first conductor layer on said substrate; forming one or more inset isolation regions in said substrate by removing portions of said first conductor layer, said first dielectric layer and said substrate underlying said first dielectric layer; filling each said inset isolation region with an isolation layer; forming a second dielectric layer on top of said first conductor layer and said isolation layers; simultaneously forming a first trench by removing a portion of each of said second dielectric layer, said first conductor layer, said first dielectric layer and said substrate underlying said first dielectric layer and forming a second trench by removing a portion of said isolation layer; forming a plurality of cavities at the bottom of said first trench by laterally removing portions of said first dielectric layer; filling each said cavity with a second conductor layer; forming a plurality of dielectric sidewalls and a dielectric bottom layer in said first trench; forming said gate electrode and said interconnect by filling said first trench and said second trench with a third conductor layer; doping said first conductor layer with dopants; and forming said raised source and said raised drain by driving said dopants into the surface region of said substrate.

Claim 14

The semiconductor device of claim 11 , wherein said process further comprises the step of forming a lightly doped well in said substrate between said step of filling the inset isolation regions and said step of forming the second dielectric layer.

Claim 15

The semiconductor device of claim 12 , wherein said step of filling said inset isolation region comprises two consecutive steps of: depositing said isolation layer on said substrate; and removing said isolation layer other than the portions filling said inset isolation region.

Claim 16

The semiconductor device of claim 13 , wherein said step of forming said inset isolation regions is carried out by anisotropic etching.

Claim 17

The semiconductor device of claim 14 , wherein said step of forming said first trench and said second trench is carried out by anisotropic etching.

Claim 18

The semiconductor device of claim 15 , wherein said step of forming said cavities in said first trench is carried out by isotropic etching.

Claim 19

The semiconductor device of claim 16 , wherein said step of filling said cavities comprises two consecutive steps of: depositing said second conductor layer on said substrate; and removing said second conductor layer other than the portions filling said cavities.

Claim 20

The semiconductor device of claim 17 , wherein said step of forming said raised source and said raised drain is carried out by annealing.

Claim 21

The semiconductor device of claim 11 , wherein said semiconductor device is a MOS transistor.

Claim 22

The semiconductor device of claim 19 , wherein said semiconductor device is a MOSFET.