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US6211005B1
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Methods of fabricating integrated circuit ferroelectric memory devices including a material layer on the upper electrodes of the ferroelectric capacitors thereof
Assignee: Samsung Electronics Co Ltd
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Filing: 1999-07-22
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Granted: 2001-04-03
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Expires: 2019-07-22
Abstract
Abstract Integrated circuit ferroelectric memory devices include an integrated circuit substrate which includes a cell region and a periphery region. A plurality of ferroelectric memory cells are formed in the cell region, including a plurality of ferroelectric capacitors. The ferroelectric capacitors each include a lower electrode, a ferroelectric layer on the lower electrode, and an upper electrode on the ferroelectric layer opposite the lower electrode. A first material layer is included on the upper electrodes in the cell region, opposite the ferroelectric layer and on the integrated circuit substrate in the peripheral region. The first material layer, which may be a semiconductor layer or an insulator layer, forms a plurality of resistors in the periphery region. Thus, a semiconductor layer or an insulator layer can be used as a resistor in the periphery region of the memory device without deteriorating the capacitor characteristics. Adhesion of the upper electrode to interconnection layers which are subsequently formed and to dielectric films which are subsequently formed can also be enhanced by the first material layer.
Inventors
- 👤 Chang-seok Kang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:02
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10D; H10D1/00; H10D1/60; H10D1/68
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
133 words
A method of fabricating an integrated circuit ferroelectric memory device, comprising the steps of: fabricating a plurality of ferroelectric memory cells in an integrated circuit substrate, the plurality of ferroelectric memory cells including a plurality of ferroelectric capacitors, the ferroelectric capacitors comprising a lower electrode, a ferroelectric layer on the lower electrode, and an upper electrode on the ferroelectric layer opposite the lower electrode; forming a first material layer on the upper electrodes opposite the ferroelectric layer that is electrically connected to the upper electrodes but is electrically insulated from the lower electrodes, wherein the first material layer has a sheet resistance of between about 5 and 500 Ω/□; forming an interlayer insulating layer on the first material layer, including a contact hole; and forming an interconnection layer on the interlayer insulating layer.
Claim 2
Independent Claim
133 words
A method of fabricating an integrated circuit ferroelectric memory device, comprising the steps of: fabricating a plurality of ferroelectric memory cells in an integrated circuit substrate, the plurality of ferroelectric memory cells including a plurality of ferroelectric capacitors, the ferroelectric capacitors comprising a lower electrode, a ferroelectric layer on the lower electrode, and an upper electrode on the ferroelectric layer opposite the lower electrode; forming a first material layer on the upper electrodes opposite the ferroelectric layer that is electrically connected to the upper electrodes but is electrically insulated from the lower electrodes, wherein the first material layer has a sheet resistance of between about 5 and 500 Ω/□; forming an interlayer insulating layer on the first material layer, including a contact hole; and forming an interconnection layer on the interlayer insulating layer.
Claim 3
Dependent Claim
37 words
A method according to claim 1 , wherein the first material layer is selected from the group consisting of tungsten silicide, SiN, TiSi x N y , TaSi x N y and Al 2 O 3 .
Claim 4
Dependent Claim
44 words
A method according to claim 1 , wherein the step of forming a first material layer is followed by the step of forming a first barrier layer on the first material layer to prevent reaction of the first material layer and the interconnection layer.
Claim 5
Dependent Claim
43 words
A method according to claim 3 , wherein the first barrier layer is selected from the group consisting of a double film of Ti/TiN, TiSi x N y , TaSi x N y , Ir, IrO 2 , Ru and RuO 2 .
Claim 6
Dependent Claim
44 words
A method according to claim 1 , wherein the following step is performed prior to the step of forming a first material layer: forming a second barrier layer on the upper electrode to prevent reaction between the upper electrode and the first material layer.
Claim 7
Dependent Claim
35 words
A method according to claim 5 , wherein the second barrier layer is selected from the group consisting of Ti/TiN, Ir, Ru, RuO 2 , TiSi x N y and TaSi x N y .
Claim 8
Dependent Claim
44 words
A method according to claim 3 , wherein the following step is performed prior to the step of forming a first material layer: forming a second barrier layer on the upper electrode to prevent reaction between the upper electrode and the first material layer.
Claim 9
Dependent Claim
29 words
A method according to claim 1 , wherein the upper and lower electrodes comprise material selected from the group consisting of a platinum group metal and a conductive oxide.
Claim 10
Dependent Claim
25 words
A method according to claim 8 , wherein the platinum group metal is selected from the group consisting of Pt, Ru, Ir, Pd and Os.
Claim 11
Dependent Claim
35 words
A method according to claim 8 , wherein the conductive oxide is selected from the group consisting of IrO 2 , platinum oxide, Osmium oxide, Indium oxide, Indium Tin Oxide (ITO) and RuO 2 .
Claim 12
Dependent Claim
38 words
A method according to claim 8 , wherein the ferroelectric layer comprises material selected from the group consisting of an oxide having Perovskite structure, Bi 4 Ti 3 O 12 and SrBi 2 Ta 2 O 9 .
Claim 13
Dependent Claim
39 words
A method according to claim 11 , wherein the oxide having Perovskite structure is selected from the group consisting of PZT, PbTiO 3 , PbLaTiO 3 , BaTiO 3 , BST (BaSrTiO 3 ) and STO (SrTiO 3 ).
Claim 14
Dependent Claim
14 words
A method according to claim 3 , wherein the first material layer comprises polysilicon.
Claim 15
Dependent Claim
15 words
A method according to claim 1 , wherein the contact hole exposes the upper electrode.
Claim 16
Dependent Claim
24 words
A method according to claim 1 , wherein the first material layer covers the entire surface of the upper electrode opposite the ferroelectric layer.
Claim 17
Independent Claim
146 words
A method of fabricating an integrated circuit ferroelectric memory device, comprising the steps of: fabricating a plurality of ferroelectric memory cells in an integrated circuit substrate, the plurality of ferroelectric memory cells including a plurality of ferroelectric capacitors, the ferroelectric capacitors comprising a lower electrode, a ferroelectric layer on the lower electrode, and an upper electrode on the ferroelectric layer opposite the lower electrode; forming a first material layer on the upper electrodes opposite the ferroelectric layer that is electrically connected to the upper electrodes, wherein the first material layer has a heat resistance of between about 5 and 500 Ω/□; and forming an interlayer insulating layer on the first material layer, including a contact hole; wherein the contact hole exposes the first material layer; and forming an interconnection layer on the interlayer insulating layer that electrically contacts the first material layer through the contact hole.
Claim 18
Independent Claim
146 words
A method of fabricating an integrated circuit ferroelectric memory device, comprising the steps of: fabricating a plurality of ferroelectric memory cells in an integrated circuit substrate, the plurality of ferroelectric memory cells including a plurality of ferroelectric capacitors, the ferroelectric capacitors comprising a lower electrode, a ferroelectric layer on the lower electrode, and an upper electrode on the ferroelectric layer opposite the lower electrode; forming a first material layer on the upper electrodes opposite the ferroelectric layer that is electrically connected to the upper electrodes, wherein the first material layer has a heat resistance of between about 5 and 500 Ω/□; and forming an interlayer insulating layer on the first material layer, including a contact hole; wherein the contact hole exposes the first material layer; and forming an interconnection layer on the interlayer insulating layer that electrically contacts the first material layer through the contact hole.
Claim 19
Independent Claim
152 words
A method of fabricating an integrated circuit ferroelectric memory device, comprising the steps of: defining a cell region and a periphery region in an integrated circuit substrate; fabricating a plurality of ferroelectric memory cells in the cell region, including a plurality of ferroelectric capacitors, the ferroelectric capacitors comprising a lower electrode, a ferroelectric layer on the lower electrode, and an upper electrode on the ferroelectric layer opposite the lower electrode; and forming a first material layer comprising material that is different from the upper electrodes, on the upper electrodes in the cell region opposite the ferroelectric layer, and on the integrated circuit substrate in the periphery region that is laterally spaced apart from the plurality of ferroelectric memory cells in the cell region, the first material layer forming a plurality of resistors in the periphery region that are laterally spaced apart form the plurality of ferroelectric memory cells in the cell region.
Claim 20
Independent Claim
152 words
A method of fabricating an integrated circuit ferroelectric memory device, comprising the steps of: defining a cell region and a periphery region in an integrated circuit substrate; fabricating a plurality of ferroelectric memory cells in the cell region, including a plurality of ferroelectric capacitors, the ferroelectric capacitors comprising a lower electrode, a ferroelectric layer on the lower electrode, and an upper electrode on the ferroelectric layer opposite the lower electrode; and forming a first material layer comprising material that is different from the upper electrodes, on the upper electrodes in the cell region opposite the ferroelectric layer, and on the integrated circuit substrate in the periphery region that is laterally spaced apart from the plurality of ferroelectric memory cells in the cell region, the first material layer forming a plurality of resistors in the periphery region that are laterally spaced apart form the plurality of ferroelectric memory cells in the cell region.
Claim 21
Dependent Claim
55 words
A method according to claim 17 , wherein the first material layer forming step is followed by the steps of: forming an interlayer insulating layer on the first material layer, including a contact hole which exposes the first material layer; and forming an interconnection layer on the interlayer insulating layer, including in the contact hole.
Claim 22
Dependent Claim
54 words
A method according to claim 17 , wherein the first material layer forming step is followed by the steps of: forming an interlayer insulating layer on the first material layer, including a contact hole which exposes the upper electrode; and forming an interconnection layer on the interlayer insulating layer, including in the contact hole.
Claim 23
Dependent Claim
29 words
A method according to claim 17 , wherein the upper and lower electrodes comprise material selected from the group consisting of a platinum group metal and a conductive oxide.
Claim 24
Dependent Claim
25 words
A method according to claim 20 , wherein the platinum group metal is selected from the group consisting of Pt, Ru, Ir, Pd and Os.
Claim 25
Dependent Claim
35 words
A method according to claim 20 , wherein the conductive oxide is selected from the group consisting of IrO 2 , platinum oxide, Osmium oxide, Indium oxide, Indium Tin Oxide (ITO) and RuO 2 .
Claim 26
Dependent Claim
38 words
A method according to claim 20 , wherein the ferroelectric layer comprises material selected from the group consisting of an oxide having Perovskite structure, Bi 4 Ti 3 O 12 and SrBi 2 Ta 2 O 9 .
Claim 27
Dependent Claim
39 words
A method according to claim 23 , wherein the oxide having Perovskite structure is selected from the group consisting of PZT, PbTiO 3 , PbLaTiO 3 , BaTiO 3 , BST (BaSrTiO 3 ) and STO (SrTiO 3 ).
Claim 28
Dependent Claim
23 words
A method according to claim 17 , wherein the first material layer has a sheet resistance of between about 5 and 500 Ω/□.
Claim 29
Dependent Claim
38 words
A method according to claim 25 , wherein the first material layer is selected from the group consisting of polysilicon, tungsten silicide, SiN, TiSi x N y , TaSi x N y and Al 2 O 3 .
Claim 30
Dependent Claim
44 words
A method according to claim 18 , wherein the step of forming a first material layer is followed by the step of forming a first barrier layer on the first material layer to prevent reaction of the first material layer and the interconnection layer.
Claim 31
Dependent Claim
43 words
A method according to claim 27 , wherein the first barrier layer is selected from the group consisting of a double film of Ti/TiN, Tisi x N y , TaSi x N y , Ir, IrO 2 , Ru and RuO 2 .
Claim 32
Dependent Claim
44 words
A method according to claim 17 , wherein the following step is performed prior to the step of forming a first material layer: forming a second barrier layer on the upper electrode to prevent reaction between the upper electrode and the first material layer.
Claim 33
Dependent Claim
35 words
A method according to claim 29 , wherein the second barrier layer is selected from the group consisting of Ti/TiN, Ir, Ru, RuO 2 , Tisi x N y and TaSi x N y .
Claim 34
Dependent Claim
44 words
A method according to claim 28 , wherein the following step is performed prior to the step of forming a first material layer: forming a second barrier layer on the upper electrode to prevent reaction between the upper electrode and the first material layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-04-02 | 2004-10-02 | 2005-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-04-02 | 2008-10-02 | 2009-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-04-02 | 2012-10-02 | 2013-04-03 | $7700.00 | Window Closed / Lapsed |