Patent US6209098B1 successfully refreshed from Google Patents.
US6209098B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit and method for ensuring interconnect security with a multi-chip integrated circuit package
Assignee: Intel Corp
•
Filing: 1998-09-21
•
Granted: 2001-03-27
•
Expires: 2018-09-21
Abstract
Abstract Circuitry implemented within a multi-chip module comprising a first integrated circuit chip and a second integrated circuit chip coupled together through an interconnect. Both the first and second integrated circuit chips include a cryptographic engine coupled to the interconnect and a non-volatile memory element used to contain key information. These cryptographic engines are solely used to encrypt outgoing information being output across the interconnect or to decrypt incoming information received from the interconnect. This prevents fraudulent physical attack of information transmitted across the interconnect.
Inventors
- 👤 Derek L. Davis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:46
CPC Classifications
H; H04; H04L; H04L9/00; G; G06; G06F; G06F12/00; G06F12/14; G06F12/1408; G06F21/00; G06F21/70; G06F21/82; G06F21/85; H04L9/06; H04L9/065; H04L9/0656; H04L9/0662; H04L9/08; H04L9/0816; H04L9/0819; H04L9/0822; H04L9/0894; G06F2207/00; G06F2207/72; G06F2207/7219; H04L2209/00; H04L2209/12
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
55 words
An apparatus comprising: an interconnect; a first integrated circuit coupled to the interconnect, the first integrated circuit including a first cryptographic engine; a second integrated circuit coupled to the interconnect, the second integrated circuit including a second cryptographic engine; and a package to contain the first integrated circuit, the second integrated circuit and the interconnect.
Claim 2
Independent Claim
55 words
An apparatus comprising: an interconnect; a first integrated circuit coupled to the interconnect, the first integrated circuit including a first cryptographic engine; a second integrated circuit coupled to the interconnect, the second integrated circuit including a second cryptographic engine; and a package to contain the first integrated circuit, the second integrated circuit and the interconnect.
Claim 3
Dependent Claim
43 words
The apparatus of claim 1 , wherein the first integrated circuit further includes a non-volatile memory element, the non-volatile memory element to contain key information to be used by the first cryptographic engine to encrypt outgoing digital information before transmission over the interconnect.
Claim 4
Dependent Claim
42 words
The apparatus of claim 1 , wherein the first integrated circuit further includes a non-volatile memory element, the non-volatile memory element to control key information to be used by the first cryptographic engine to decrypt incoming digital information received over the interconnect.
Claim 5
Dependent Claim
44 words
The apparatus according to claim 1 , wherein the second integrated circuit further includes a non-volatile memory element, the non-volatile memory element to contain key information to be used by the second cryptographic engine to encrypt outgoing digital information before transmission over the interconnect.
Claim 6
Dependent Claim
31 words
The apparatus of claim 1 , wherein the non-volatile memory to contain key information to be used by the second integrated circuit to decrypt incoming digital information received over the interconnect.
Claim 7
Dependent Claim
31 words
The apparatus of claim 1 , wherein the first integrated circuit to execute a stream cipher algorithm to encrypt the outgoing digital information and alternatively to decrypt the incoming digital information.
Claim 8
Dependent Claim
67 words
The apparatus of claim 1 , wherein the first integrated circuit includes logic circuitry and an on-chip, non-volatile memory element, the on-chip, non-volatile memory element to contain key information to be used by the first cryptographic engine to establish a session key used to encrypt digital information before transmission over the interconnect and to decrypt incoming digital information received by the first cryptographic engine over the interconnect.
Claim 9
Dependent Claim
15 words
The apparatus of claim 7 further including a random number generator contained in the package.
Claim 10
Dependent Claim
22 words
The apparatus of claim 8 , wherein the random number generator to generate information used to produce at least the key information.
Claim 11
Dependent Claim
14 words
The apparatus of claim 1 , wherein the package includes a multi-chip semiconductor package.
Claim 12
Dependent Claim
27 words
The apparatus of claim 1 , wherein the package includes a circuit board upon which both the first integrated circuit and the second integrated circuit are mounted.
Claim 13
Dependent Claim
14 words
The apparatus of claim 1 , wherein the first integrated circuit includes a processor.
Claim 14
Dependent Claim
14 words
The apparatus of claim 12 , wherein the second integrated circuit includes non-volatile memory.
Claim 15
Dependent Claim
67 words
A computer system comprising: a memory element; and a processing unit coupled to the memory element, the processing unit including a first integrated circuit including a first cryptographic engine, a second integrated circuit including a second cryptographic engine, an interconnect coupled to both the first integrated circuit and the second integrated circuit, and a package containing the first integrated circuit, the second integrated circuit and the interconnect.
Claim 16
Dependent Claim
67 words
A computer system comprising: a memory element; and a processing unit coupled to the memory element, the processing unit including a first integrated circuit including a first cryptographic engine, a second integrated circuit including a second cryptographic engine, an interconnect coupled to both the first integrated circuit and the second integrated circuit, and a package containing the first integrated circuit, the second integrated circuit and the interconnect.
Claim 17
Dependent Claim
40 words
The computer system of claim 14 , wherein the first integrated circuit of the processing unit including a first internal memory element to contain key information used by the first cryptographic engine to encrypt outgoing digital information over the interconnect.
Claim 18
Dependent Claim
27 words
The computer system of claim 15 , wherein the first cryptographic engine of the first integrated circuit to decrypt incoming digital information received by the processing unit.
Claim 19
Dependent Claim
36 words
The computer system according to claim 15 , wherein the first integrated circuit of the processing unit to execute a stream cipher algorithm to encrypt the outgoing digital information and alternatively to decrypt incoming digital information.
Claim 20
Dependent Claim
63 words
The computer system according to claim 16 , wherein the first integrated circuit of the processing unit includes a processor core, including the first cryptographic engine and the first internal memory element, to contain key information to be used by the first cryptographic engine to establish a session key used to encrypt the outgoing digital information and to decrypt the incoming digital information.
Claim 21
Dependent Claim
41 words
The computer system of claim 14 , wherein the second integrated circuit of the processing unit includes a non-volatile memory element, the non-volatile memory element to contain key information used by the second cryptographic engine to encrypt the outgoing digital information.
Claim 22
Dependent Claim
26 words
The computer system of claim 14 , wherein the second cryptographic engine of the second integrated circuit to decrypt incoming digital information received over the interconnect.
Claim 23
Independent Claim
91 words
A method of transferring digital information between a first integrated circuit and a second integrated circuit implemented within a multi-chip module, the method comprising: generating a session key by the first integrated circuit; encrypting the session key with a symmetric key stored in a non-volatile memory element of the first integrated circuit to produce a message; and outputting the message for decryption by the symmetric key stored in the second integrated circuit to retrieve the session key used for subsequent communications between the first integrated circuit and the second integrated circuit.
Claim 24
Independent Claim
91 words
A method of transferring digital information between a first integrated circuit and a second integrated circuit implemented within a multi-chip module, the method comprising: generating a session key by the first integrated circuit; encrypting the session key with a symmetric key stored in a non-volatile memory element of the first integrated circuit to produce a message; and outputting the message for decryption by the symmetric key stored in the second integrated circuit to retrieve the session key used for subsequent communications between the first integrated circuit and the second integrated circuit.
Claim 25
Independent Claim
112 words
A method for initialization of a multi-chip module having at least two integrated circuit chips connected together by an interconnect, the method comprising: implementing a static key into a first integrated circuit chip and a second integrated circuit chip; packaging the first integrated circuit chip and the second integrated circuit chip into the multi-chip module; powering the first integrated circuit to randomly generate a key is loaded into the first integrated circuit; encrypting the key with the static key to produce a message; and transferring the message to the second integrated circuit to recover the key, the key used to secure communications between the first integrated circuit and the second integrated circuit.
Claim 26
Independent Claim
112 words
A method for initialization of a multi-chip module having at least two integrated circuit chips connected together by an interconnect, the method comprising: implementing a static key into a first integrated circuit chip and a second integrated circuit chip; packaging the first integrated circuit chip and the second integrated circuit chip into the multi-chip module; powering the first integrated circuit to randomly generate a key is loaded into the first integrated circuit; encrypting the key with the static key to produce a message; and transferring the message to the second integrated circuit to recover the key, the key used to secure communications between the first integrated circuit and the second integrated circuit.
References Cited (Backward Citations)
US4092524A
Cited
US4271482A
Cited
US4310720A
Cited
US4471216A
Cited
US4638120A
Cited
US4467139A
Cited
US4656474A
Cited
US4544833A
Cited
US4549075A
Cited
US4656342A
Cited
US4907270A
Cited
US4907272A
Cited
US4910774A
Cited
US5396609A
Cited
US5068894A
Cited
US5428685A
Cited
US5596718A
Cited
US5559883A
Cited
US5377264A
Cited
US5483596A
Cited
US5539828A
Cited
US5796840A
Cited
US5805712A
Cited
US5530753A
Cited
US5473692A
Cited
US5568552A
Cited
US5615263A
Cited
US5805706A
Cited
US5828753A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-03-26 | 2004-09-25 | 2005-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-03-26 | 2008-09-25 | 2009-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-03-26 | 2012-09-25 | 2013-03-27 | $7700.00 | Window Closed / Lapsed |