US5828753A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit and method for ensuring interconnect security within a multi-chip integrated circuit package
Assignee: Intel Corp
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Filing: 1996-10-25
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Granted: 1998-10-27
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Expires: 2016-10-25
Abstract
Abstract Circuitry implemented within a multi-chip module comprising a first integrated circuit chip and a second integrated circuit chip coupled together through an interconnect. Both the first and second integrated circuit chips include a cryptographic engine coupled to the interconnect and a non-volatile memory element used to contain key information. These cryptographic engines are solely used to encrypt outgoing information being output across the interconnect or to decrypt incoming information received from the interconnect. This prevents fraudulent physical attack of information transmitted across the interconnect.
Inventors
- 👤 Derek L. Davis
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:19
CPC Classifications
H; H04; H04L; H04L9/00; G; G06; G06F; G06F12/00; G06F12/14; G06F12/1408; G06F21/00; G06F21/70; G06F21/82; G06F21/85; H04L9/06; H04L9/065; H04L9/0656; H04L9/0662; H04L9/08; H04L9/0816; H04L9/0819; H04L9/0822; H04L9/0894; G06F2207/00; G06F2207/72; G06F2207/7219; H04L2209/00; H04L2209/12
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
59 words
A multi-chip module comprising: an interconnect; a first integrated circuit chip including a first cryptographic engine, the first cryptographic engine being coupled to the interconnect; a second integrated circuit chip including a second cryptographic engine, the second cryptographic engine being coupled to the interconnect; and a package containing the first integrated circuit chip and the second integrated circuit chip.
Claim 2
Dependent Claim
59 words
A multi-chip module comprising: an interconnect; a first integrated circuit chip including a first cryptographic engine, the first cryptographic engine being coupled to the interconnect; a second integrated circuit chip including a second cryptographic engine, the second cryptographic engine being coupled to the interconnect; and a package containing the first integrated circuit chip and the second integrated circuit chip.
Claim 3
Dependent Claim
62 words
The multi-chip module according to claim 1, wherein the first integrated circuit chip further includes a non-volatile memory element, the non-volatile memory element to contain key information to be used by the first cryptographic engine for encryption of outgoing digital information before transmission over the interconnect and for decryption of incoming digital information received by the first cryptographic engine over the interconnect.
Claim 4
Dependent Claim
62 words
The multi-chip module according to claim 1, wherein the second integrated circuit chip further includes a non-volatile memory element, the non-volatile memory element to contain key information to be used by the second cryptographic engine for encryption of outgoing digital information before transmission over the interconnect and for decryption of incoming digital information received by the second cryptographic engine over the interconnect.
Claim 5
Dependent Claim
33 words
The multi-chip module according to claim 1, wherein the first integrated circuit chip to execute a stream cipher algorithm to encrypt the outgoing digital information and alternatively to decrypt the incoming digital information.
Claim 6
Dependent Claim
40 words
The multi-chip module according to claim 1, wherein the first cryptographic engine is dedicated to perform cryptographic operations on the outgoing digital information before transmission through the interconnect, and alternatively on the incoming digital information upon receipt over the interconnect.
Claim 7
Dependent Claim
75 words
The multi-chip module according to claim 1, wherein the first integrated circuit chip includes logic circuitry and an on-chip, non-volatile memory element, the on-chip, non-volatile memory element to contain key information to be used by the first cryptographic engine to establish a session key used to encrypt digital information before transferring to the second integrated circuit chip over the interconnect and to decrypt incoming digital information received by the first cryptographic engine over the interconnect.
Claim 8
Dependent Claim
13 words
The multi-chip module according to claim 6 further including a random number generator.
Claim 9
Dependent Claim
18 words
The multi-chip module according to claim 7, wherein the random number generator produces at least the key information.
Claim 10
Dependent Claim
18 words
The multi-chip module according to claim 6, wherein the second integrated circuit chip includes memory and support logic.
Claim 11
Dependent Claim
109 words
An electronic device encapsulated within a multi-chip module, the electronic device comprising: first circuit means for processing information, the first circuit means including logic for encrypting outgoing digital information prior to transmission for decrypting incoming digital information after receipt; second circuit means for storing information, the second circuit means including logic for encrypting the second set of digital information prior to outputting digital information to the first circuit means and for decrypting outgoing digital information from the first circuit means after receipt; connection means for interconnecting the first circuit means with the second circuit means; and packaging means for containing the first circuit means and the second circuit means.
Claim 12
Dependent Claim
109 words
An electronic device encapsulated within a multi-chip module, the electronic device comprising: first circuit means for processing information, the first circuit means including logic for encrypting outgoing digital information prior to transmission for decrypting incoming digital information after receipt; second circuit means for storing information, the second circuit means including logic for encrypting the second set of digital information prior to outputting digital information to the first circuit means and for decrypting outgoing digital information from the first circuit means after receipt; connection means for interconnecting the first circuit means with the second circuit means; and packaging means for containing the first circuit means and the second circuit means.
Claim 13
Dependent Claim
50 words
The electronic device according to claim 10, wherein the first circuit means includes a first cryptographic engine and a first internal memory storing key information used for encrypting the outgoing digital information before transmission to the second circuit means and alternatively decrypting the digital information from the second circuit means.
Claim 14
Dependent Claim
18 words
The electronic device according to claim 11, wherein the first circuit means further includes a random number generator.
Claim 15
Dependent Claim
49 words
The electronic device according to claim 11, wherein the second circuit means includes a second cryptographic engine and a second internal memory storing key information used for encrypting the digital information output to the first circuit means and alternatively decrypting the outgoing digital information from the first circuit means.
Claim 16
Dependent Claim
98 words
A computer system comprising: a memory element; and a central processing unit coupled to the memory element, the central processing unit, being packaged as a multi-chip module, including a first integrated circuit chip including a first cryptographic engine and a first internal memory element, a second integrated circuit chip including a second internal memory element and control logic including at least a second cryptographic engine, an interconnect coupled to both the first integrated circuit chip and the second integrated circuit chip, and a package containing the first integrated circuit chip, the second integrates circuit chip, and the interconnect.
Claim 17
Dependent Claim
98 words
A computer system comprising: a memory element; and a central processing unit coupled to the memory element, the central processing unit, being packaged as a multi-chip module, including a first integrated circuit chip including a first cryptographic engine and a first internal memory element, a second integrated circuit chip including a second internal memory element and control logic including at least a second cryptographic engine, an interconnect coupled to both the first integrated circuit chip and the second integrated circuit chip, and a package containing the first integrated circuit chip, the second integrates circuit chip, and the interconnect.
Claim 18
Dependent Claim
61 words
The computer system according to claim 14, wherein the first internal memory element of the first integrated circuit chip includes an on-chip cache to contain key information to be used by the first cryptographic engine for encryption of outgoing digital information transmission over the interconnect and for decryption of incoming digital information received by the first cryptographic engine over the interconnect.
Claim 19
Dependent Claim
62 words
The computer system according to claim 14, wherein the second integrated circuit chip further includes a non-volatile memory element, the non-volatile memory element to contain key information to be used by the second cryptographic engine for encryption of outgoing digital information before transmission over the interconnect and for decryption of incoming digital information received by the second cryptographic engine over the interconnect.
Claim 20
Dependent Claim
23 words
The computer system according to claim 16, wherein the second internal memory element of the second integrated circuit chip includes an off-chip cache.
Claim 21
Dependent Claim
38 words
The computer system according to claim 14, wherein the first integrated circuit chip of the central processing unit to execute a stream cipher algorithm to encrypt the outgoing digital information and alternatively to decrypt the incoming digital information.
Claim 22
Dependent Claim
40 words
The computer system according to claim 14, wherein the first cryptographic engine is dedicated to performing cryptographic operations on the outgoing digital information before transmission through the interconnect, and alternatively, on the incoming digital information upon receipt over the interconnect.
Claim 23
Dependent Claim
78 words
The computer system according to claim 17, wherein the first integrated circuit chip includes a processor core including the first cryptographic engine and the first internal memory element that to contain key information to be used by the first cryptographic engine to establish a session key used to encrypt outgoing digital information before transmission to the second integrated circuit chip over the interconnect, and to decrypt incoming digital information received by the first cryptographic engine over the interconnect.
Claim 24
Dependent Claim
18 words
The computer system according to claim 20, wherein the first integrated circuit chip includes a random number generator.
Claim 25
Independent Claim
116 words
A method of transferring digital information between a first and second integrated circuit chips interconnected by an interconnect and implemented within a multi-chip module, the method comprising generating a session key by the first integrated circuit chip; encrypting the session key with a symmetric key stored in a non-volatile memory element of the first integrated circuit chip at manufacture to produce a message; transferring the message through the interconnect; decrypting the message with the symmetric key stored in a non-volatile memory element of the second integrated circuit chip to retrieve the session key; and utilizing the session key for communications between the first integrated circuit chip and the second integrated circuit chip of the multi-chip module.
Claim 26
Independent Claim
116 words
A method of transferring digital information between a first and second integrated circuit chips interconnected by an interconnect and implemented within a multi-chip module, the method comprising generating a session key by the first integrated circuit chip; encrypting the session key with a symmetric key stored in a non-volatile memory element of the first integrated circuit chip at manufacture to produce a message; transferring the message through the interconnect; decrypting the message with the symmetric key stored in a non-volatile memory element of the second integrated circuit chip to retrieve the session key; and utilizing the session key for communications between the first integrated circuit chip and the second integrated circuit chip of the multi-chip module.
Claim 27
Independent Claim
141 words
A method for initialization of a multi-chip module having at least two integrated circuit chips connected together by an interconnect, the method comprising: implementing static key into masks of a first integrated chip and a second integrated circuit chip; packaging the first integrated circuit chip and the second integrated circuit chip into the multi-chip module; powering the first integrated circuit chip and the second integrated circuit chip so that a randomly generated key is loaded into the first integrated circuit chip; encrypting the randomly generated key with the static key to produce a message; transferring the message to the second integrated circuit chip; decrypting the message to retrieve the randomly generated key; and utilizing the randomly generated key by both the first integrated circuit chip and the second integrated circuit chip to exchange session keys for secured communication over the interconnect.
Claim 28
Independent Claim
141 words
A method for initialization of a multi-chip module having at least two integrated circuit chips connected together by an interconnect, the method comprising: implementing static key into masks of a first integrated chip and a second integrated circuit chip; packaging the first integrated circuit chip and the second integrated circuit chip into the multi-chip module; powering the first integrated circuit chip and the second integrated circuit chip so that a randomly generated key is loaded into the first integrated circuit chip; encrypting the randomly generated key with the static key to produce a message; transferring the message to the second integrated circuit chip; decrypting the message to retrieve the randomly generated key; and utilizing the randomly generated key by both the first integrated circuit chip and the second integrated circuit chip to exchange session keys for secured communication over the interconnect.
Claim 29
Dependent Claim
15 words
The multi-chip module of claim 1, wherein the first integrated circuit chip includes a processor.
Claim 30
Dependent Claim
15 words
The multi-chip module of claim 24, wherein the second integrated circuit chip includes non-volatile memory.
Claim 31
Dependent Claim
14 words
The multi-chip module of claim 1, wherein the package includes a multi-chip semiconductor package.
Claim 32
Dependent Claim
29 words
The multi-chip module of claim 1, wherein the package includes a circuit board upon which both the first integrated circuit chip and the second integrated circuit chip are mounted.
Claim 33
Dependent Claim
13 words
The multi-chip module of claim 1, wherein the package further contains the interconnect.
References Cited (Backward Citations)
US5396609A
Cited
US5428685A
Cited
US5596718A
Cited
US5559883A
Cited
US5377264A
Cited
US5483596A
Cited
US5615263A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-10-26 | 2002-04-27 | 2002-10-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-10-26 | 2006-04-27 | 2006-10-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-10-26 | 2010-04-27 | 2010-10-27 | $7700.00 | Window Closed / Lapsed |