Pulse amplifier with low duty cycle errors

Claim 2

A pulse amplifier comprising a first input for receiving an input signal containing frequencies, a feedback input, an output, a plurality of fully differential amplifier stages between said inputs and said output, and an offset canceling feedback network between said output and said feedback input comprising an amplifier and a low pass filter having a cut-off frequency below said frequencies contained in said input signal.

Claim 3

A pulse amplifier as claimed in claim 1 , wherein each fully differential amplifier stage comprises first and second transistors forming a differential pair and having a common node, and a pair of load transistors for said respective first and second transistors.

Claim 4

A pulse amplifier as claimed in claim 2 , wherein at least one of said stages comprises a limiting circuit for limiting a voltage swing of said common node thereof.

Claim 5

A pulse amplifier as claimed in claim 3 , wherein in the presence of large input signals causing one of said first and second transistors to be driven hard into conduction, said limiting circuit reduces current flow through said conducting one of said first and second transistors.

Claim 6

A pulse amplifier as claimed in claim 4 , wherein said limiting circuit comprises cascode transistors in series with said respective first and second transistors, whereby in the presence of large input signals, the current flow through the cascode transistor in series with said conducting one of said first and second transistors is reduced.

Claim 7

A pulse amplifier as claimed in claim 5 , wherein said transistors are field effect transistors.

Claim 8

A pulse amplifier as claimed in claim 6 , wherein said field effect transistors transistors have first and second main electrodes, and a gate electrode, and the second main electrodes of said first and second transistors are connected to the first main electrodes of said respective cascode transistors, and wherein in the presence of large input signals, said common node is substantially shorted to the first main electrode of said cascode transistor which is connected to the second main electrode of said one conducting transistor, and said current through said cascode transistor in series with said conducting one transistor is gradually reduced as the voltage of the first main electrode thereof approaches the gate voltage voltage thereof.

Claim 9

A pulse amplifier as claimed in claim 7 , wherein said first and second transistors each have a saturation voltage, and said cascode transistors hold a voltage between said first main electrode and said second main electrode of each of said first and second transistors substantially constant above said saturation voltage for each of said first and second transistors as long as the amplifier stage is not clipping due to large input signals.

Claim 10

A pulse amplifier as claimed in claim 8 , wherein said first main electrode is the source, and said second main electrode is the drain.

Claim 11

A pulse amplifier as claimed in claim 8 , wherein said load transistors are in parallel with said first and second transistors.

Claim 12

A pulse amplifier as claimed in claim 10 , further comprising first and second respective current sources in series with said cascode transistors, and a third current source in series with said common node.

Claim 13

A pulse amplifier as claimed in claim 11 , wherein said first and second current sources provide a current larger than a current provided by said third current source to ensure that current flows through said load transistors even when said first and second transistors are saturated.

Claim 14

A pulse amplifier as claimed in claim 11 , further comprising a biasing network for generating bias voltages for said current sources and said cascode transistors.

Claim 15

A pulse amplifier as claimed in claim 13 , wherein the load transistors are of the same type as said differential transistors.

Claim 16

A pulse amplifier as claimed in claim 11 , wherein said third current source is variable to provide said amplifier stages with variable gain.

Claim 19

A method as claimed in claim 16 , wherein said amplifier stages comprise first and second transistors forming a differential pair connected to a common node, and a pair of load transistors for said respective first and second transistors, one of said first and second transistors being driven hard into conduction in the presence of large input signals, and current flow through conducting one of said first and second transistors is reduced for large input signals.

Claim 20

A method as claimed in claim 17 , wherein said load transistors are arranged in parallel with said respective first and second transistors.

Claim 21

A method as claimed in claim 18 , wherein said first and second transistors and said load transistors are connected to a common supply rail.

Claim 22

A method as claimed in claim 18 , wherein a pair of cascode transistors are connected in series with said respective first and second transistors, first and second respective current sources are connected in series with said cascode transistors, and a third current source in series with said common node, said first and second current sources supplying a greater current than said third current source to ensure that current flows through said load transistors when said first and second transistors are saturated.

Claim 23

A method as claimed in claim 20 , wherein an offset cancellation feedback signal is fed back to the input.

Claim 24

A method as claimed in claim 21 , wherein when the amplifier is powered on, the offset cancellation feedback signal is held at a voltage near the dc input voltage while the amplifier is disabled to reduce start-up time.

Claim 25

A pulse amplifier comprising a first input for receiving an input signal containing frequencies, a feedback input, an output, a plurality of fully differential amplifier stages between said inputs and said output, each fully differential amplifier stage comprising first and second transistors forming a differential pair and having a common node, a pair of load transistors for said respective first and second transistors, and first and said cascode transistors in series with said first and second transistors for reducing the current through one of said first and second transistors driven into conduction in the presence of large input signals to limit the voltage swing of said common node, and an offset canceling feedback network between said output and said feedback input comprising an amplifier and a low pass filter having a cut-off frequency below said frequencies contained in said input signal.

Claim 26

A pulse amplifier comprising a first input for receiving an input signal containing frequencies, a feedback input, an output, a plurality of fully differential amplifier stages between said inputs and said output, each fully differential amplifier stage comprising first and second transistors forming a differential pair and having a common node, a pair of load transistors for said respective first and second transistors, and first and said cascode transistors in series with said first and second transistors for reducing the current through one of said first and second transistors driven into conduction in the presence of large input signals to limit the voltage swing of said common node, and an offset canceling feedback network between said output and said feedback input comprising an amplifier and a low pass filter having a cut-off frequency below said frequencies contained in said input signal.

Claim 27

A pulse amplifier as claimed in claim 23 , wherein said load transistors are in parallel with said transistors of said differential pair.

Claim 28

A pulse amplifier comprising a first input for receiving an input signal containing frequencies, a feedback input, an output, a plurality of fully differential amplifier stages between said inputs and said output arranged to ensure more symmetrical delays in positive and negative directions of the input signals, each fully differential amplifier stage comprising first and second transistors forming a differential pair and having a common node, a pair of load transistors in parallel with said respective first and second transistors, and an offset canceling feedback network between said output and said feedback input comprising an amplifier and a low pass filter having a cut-off frequency below said frequencics contained in said input signal.

Claim 29

A pulse amplifier comprising a first input for receiving an input signal containing frequencies, a feedback input, an output, a plurality of fully differential amplifier stages between said inputs and said output arranged to ensure more symmetrical delays in positive and negative directions of the input signals, each fully differential amplifier stage comprising first and second transistors forming a differential pair and having a common node, a pair of load transistors in parallel with said respective first and second transistors, and an offset canceling feedback network between said output and said feedback input comprising an amplifier and a low pass filter having a cut-off frequency below said frequencics contained in said input signal.