Patent US6207987B1 successfully refreshed from Google Patents.
← Back to Patent Explorer
US6207987B1 Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device having smooth surface for suppressing layer displacement

Assignee: Renesas Electronics Corp
•
Filing: 1998-11-24
•
Granted: 2001-03-27
•
Expires: 2018-11-24
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract On a silicon oxide film covering a gate electrode portion, a reflowed and polished BPSG film is formed. A second interconnection layer is formed on the BPSG film. To cover the second interconnection layer, a silicon oxide film having a thickness of at least the substantial thickness of the second interconnection layer is formed on a silicon oxide film. Thus, the planarity of the base of the interconnection layer is ensured and displacement of the interconnection layer is suppressed. Accordingly, a semiconductor device having a high degree of integration is obtained.

Inventors

  • 👤 Isao Tottori

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 16:25
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/092; H10W20/074; H10W20/077

Claims Analysis

Total Claims: 22
Claim 1
Independent Claim 127 words
A semiconductor device, comprising: a semiconductor substrate having a main surface; a first interconnection layer formed on said semiconductor substrate; a first interlayer insulating film formed on said semiconductor substrate to cover said first interconnection layer, said first interlayer being polished by chemical-mechanical polishing; a second interconnection layer formed on said first interlayer insulating film; and a second interlayer insulating film formed on said first interlayer insulating film to cover said second interconnection layer; said first interlayer insulating film has one of a polished top surface and a film having a polished top surface which is laminated on said first interlayer insulating film, the polished top surface defining means for preventing displacement of said second interconnection layer when said first interlayer insulating film is transformed by heat.
Claim 2
Dependent Claim 127 words
A semiconductor device, comprising: a semiconductor substrate having a main surface; a first interconnection layer formed on said semiconductor substrate; a first interlayer insulating film formed on said semiconductor substrate to cover said first interconnection layer, said first interlayer being polished by chemical-mechanical polishing; a second interconnection layer formed on said first interlayer insulating film; and a second interlayer insulating film formed on said first interlayer insulating film to cover said second interconnection layer; said first interlayer insulating film has one of a polished top surface and a film having a polished top surface which is laminated on said first interlayer insulating film, the polished top surface defining means for preventing displacement of said second interconnection layer when said first interlayer insulating film is transformed by heat.
Claim 3
Dependent Claim 40 words
The semiconductor device according to claim 1 , wherein said first interlayer insulating film includes an impurity-doped insulating film that contains prescribed impurities and is reflowed, and wherein the polished top surface is formed on the reflowed impurity-doped insulating film.
Claim 4
Dependent Claim 45 words
The semiconductor device according to claim 2 , wherein an insulating film which is free of the prescribed impurities is formed over one of a top surface and under a bottom surface of the impurity-doped insulating film forming part of said first interlayer insulating film.
Claim 5
Dependent Claim 24 words
The semiconductor device according to claim 2 , wherein said first interlayer insulating film includes a substrate coating insulating film covering said semiconductor substrate.
Claim 6
Dependent Claim 62 words
The semiconductor device according to claim 1 , wherein said first interlayer insulating film includes: an impurity-doped insulating film that contains prescribed impurities and which is reflowed, and a non-impurity-doped insulating film that is formed on said reflowed impurity-doped insulating film and which does not contain said prescribed impurities, and wherein the polished top surface is formed on the non-impurity-doped insulating film.
Claim 7
Dependent Claim 40 words
The semiconductor device according to claim 5 , further comprising an insulating film which is free of the prescribed impurities and which is formed over one of a top surface and under a bottom surface of said impurity-doped insulating film.
Claim 8
Dependent Claim 24 words
The semiconductor device according to claim 5 , wherein said first interlayer insulating film includes a substrate coating insulating film covering said semiconductor substrate.
Claim 9
Dependent Claim 38 words
The semiconductor device according to claim 1 , wherein said first interlayer insulating film includes a non-impurity-doped insulating film that is free of prescribed impurities, and wherein the polished top surface is formed on the non-impurity-doped insulating film.
Claim 10
Dependent Claim 55 words
The semiconductor device according to claim 8 , wherein: said first interlayer insulating film includes a first dipped insulating film formed on said semiconductor substrate by a Spin-On-Glass method to fill a space between two adjacent interconnections included said first interconnection layers, and said non-impurity-doped insulating film is formed on said first dipped insulating film.
Claim 11
Dependent Claim 50 words
The semiconductor device according to claim 1 , wherein said second interlayer insulating film includes an interconnection coating insulating film that has a thickness sufficient to enable fixing and holding of said second interconnection layer in position on said first interlayer insulating film and which covers said second interconnection layer.
Claim 12
Dependent Claim 52 words
The semiconductor device according to claim 1 , wherein said second interlayer insulating film includes a second dipped insulting film formed on said first interlayer insulating film by a Spin-On-Glass method to fill a space between two adjacent interconnections included in said second interconnection layer or to cover said second interconnection layer.
Claim 13
Dependent Claim 31 words
The semiconductor device according to claim 11 , wherein said second interlayer insulating film includes an interconnection protecting film formed between said second interconnection layer and said second dipped insulating film.
Claim 14
Dependent Claim 26 words
The semiconductor device according to claim 1 , wherein said second interlayer insulating film includes a film having a top surface that is polished or reflowed.
Claim 15
Dependent Claim 114 words
A semiconductor device, comprising: a semiconductor substrate having a main surface; a first interconnection layer formed on said semiconductor substrate; a first interlayer insulating film formed on said semiconductor substrate to cover said first interconnection layer; a second interconnection layer formed on said first interlayer insulating film; and a second interlayer insulating film formed on said first interlayer insulating film to cover said second interconnection layer; said first interlayer insulating film including an impurity-doped insulating film that contains prescribed impurities and is reflowed, and said second interlayer insulating film having an interconnection coating insulating film that has a thickness allowing fixing and holding of said second interconnection layer and covers said second interconnection layer.
Claim 16
Dependent Claim 114 words
A semiconductor device, comprising: a semiconductor substrate having a main surface; a first interconnection layer formed on said semiconductor substrate; a first interlayer insulating film formed on said semiconductor substrate to cover said first interconnection layer; a second interconnection layer formed on said first interlayer insulating film; and a second interlayer insulating film formed on said first interlayer insulating film to cover said second interconnection layer; said first interlayer insulating film including an impurity-doped insulating film that contains prescribed impurities and is reflowed, and said second interlayer insulating film having an interconnection coating insulating film that has a thickness allowing fixing and holding of said second interconnection layer and covers said second interconnection layer.
Claim 17
Dependent Claim 27 words
The semiconductor device according to claim 14 , wherein said interconnection coating insulating film has a thickness of at least a thickness of said second interconnection layer.
Claim 18
Dependent Claim 28 words
The semiconductor device according to claim 14 , wherein said second interlayer insulating film includes a film having a top surface that is one of polished and reflowed.
Claim 19
Dependent Claim 45 words
The semiconductor device according to claim 14 , wherein said interconnection coating insulating film includes a dipped insulating film formed by a Spin-On-Glass method to fill a space between two adjacent interconnections included in said second interconnection layers or to cover said second interconnection layer.
Claim 20
Dependent Claim 31 words
The semiconductor device according to claim 17 , wherein said second interlayer insulating film includes an interconnection protecting film formed between said second interconnection layer and the third dipped insulating film.
Claim 21
Dependent Claim 37 words
The semiconductor device according to claim 14 , wherein an insulating film that is free of said prescribed impurities is formed over one of a top surface and under a bottom surface of said impurity-doped insulating film.
Claim 22
Dependent Claim 24 words
The semiconductor device according to claim 14 , wherein said first interlayer insulating film includes a substrate coating insulating film covering said semiconductor substrate.

References Cited (Backward Citations)

JPH0851108A Cited
US5717236A Cited
US5936272A Cited
US5550076A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2004-03-26 2004-09-25 2005-03-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2008-03-26 2008-09-25 2009-03-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2012-03-26 2012-09-25 2013-03-27 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag