US6207490B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device and method for fabricating the same
Assignee: Samsung Electronics Co Ltd
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Filing: 1998-12-10
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Granted: 2001-03-27
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Expires: 2018-12-10
Abstract
Abstract There are provided a semiconductor device and a fabricating method thereof, in which a plurality of buried diffusion layers repeatedly extend on a semiconductor substrate and a plurality of word lines repeatedly extend on the buried diffusion layers, perpendicularly to the buried diffusion layers. The cross-sections of the word lines are shaped in asymmetrical polygons, with odd-numbered word lines having the same cross-section and the even-numbered word lines having the same cross-section. Narrow gate electrodes can be formed on the buried diffusion layers, using a spacer mask, so that the area of a memory cell array can be reduced by 50% and thus a cell integration level can be increased.
Inventors
- 👤 Woon-kyung Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:05
CPC Classifications
H; H10; H10P; H10P54/00; H10D; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01304; H10D64/01324; H10B; H10B99/00; H10D64/01326; H10D64/01328; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D84/02; H10D84/03; H10D84/038; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
52 words
A semiconductor device comprising: a plurality of buried diffusion layers repeatedly extending on a semiconductor substrate; and a plurality of word lines repeatedly extending over the buried diffusion layers perpendicularly thereto, and having asymmetrical polygonal cross-sections, with odd-numbered word lines having the same cross-section and even-numbered word lines having the same cross-section.
Claim 2
Dependent Claim
52 words
A semiconductor device comprising: a plurality of buried diffusion layers repeatedly extending on a semiconductor substrate; and a plurality of word lines repeatedly extending over the buried diffusion layers perpendicularly thereto, and having asymmetrical polygonal cross-sections, with odd-numbered word lines having the same cross-section and even-numbered word lines having the same cross-section.
Claim 3
Dependent Claim
64 words
A semiconductor device comprising: a plurality of buried diffusion layers extending on a semiconductor substrate; and a plurality of word lines extending perpendicular to the buried diffusion layers and having asymmetrical polygonal cross-sections, odd-numbered word lines having a first cross-section and even-numbered word lines having a second cross-section; wherein the odd-numbered word lines have a mirror symmetry with respect to the even-numbered word lines.
Claim 4
Dependent Claim
64 words
A semiconductor device comprising: a plurality of buried diffusion layers extending on a semiconductor substrate; and a plurality of word lines extending perpendicular to the buried diffusion layers and having asymmetrical polygonal cross-sections, odd-numbered word lines having a first cross-section and even-numbered word lines having a second cross-section; wherein the odd-numbered word lines have a mirror symmetry with respect to the even-numbered word lines.
Claim 5
Dependent Claim
129 words
A semiconductor device having a memory cell array region and a peripheral circuit region for driving a cell comprising: a plurality of buried diffusion layers repeatedly extending on a semiconductor substrate, as bit lines and sources/drains of cell transistors in the memory cell array region; and a plurality of word lines repeatedly extending as gate electrodes of the cell transistors on the substrate having the buried diffusion layer formed thereon in the memory cell array region, perpendicularly to the buried diffusion layers, wherein the gate electrodes of the cell transistors in the memory cell array region have asymmetrical polygonal cross-sections, and the deposition structure on the gate electrodes of the cell transistors is different from that on gate electrodes of peripheral circuit transistors formed in the peripheral circuit region.
Claim 6
Dependent Claim
129 words
A semiconductor device having a memory cell array region and a peripheral circuit region for driving a cell comprising: a plurality of buried diffusion layers repeatedly extending on a semiconductor substrate, as bit lines and sources/drains of cell transistors in the memory cell array region; and a plurality of word lines repeatedly extending as gate electrodes of the cell transistors on the substrate having the buried diffusion layer formed thereon in the memory cell array region, perpendicularly to the buried diffusion layers, wherein the gate electrodes of the cell transistors in the memory cell array region have asymmetrical polygonal cross-sections, and the deposition structure on the gate electrodes of the cell transistors is different from that on gate electrodes of peripheral circuit transistors formed in the peripheral circuit region.
Claim 7
Dependent Claim
159 words
A semiconductor device having a memory cell array region and a peripheral circuit region for driving a cell, the memory cell array region having a plurality of cell transistors, the device comprising: a plurality of buried diffusion layers extending on a semiconductor substrate, the diffusion layers forming bit lines, source regions, and drain regions of the plurality of cell transistors; and a plurality of word lines extending perpendicularly to the plurality of buried diffusion layers, the plurality of word lines forming gate electrodes of the plurality of cell transistors, wherein the gate electrodes of the cell transistors have asymmetrical and polygonal cross-sections; and deposition structures on the gate electrodes of the cell transistors is different from deposition structures on gate electrodes of peripheral circuit transistors formed in the peripheral circuit region; wherein each of the gate electrodes of the cell transistors formed in the memory cell array region have a mirror symmetry with respect to an adjacent gate electrode.
Claim 8
Dependent Claim
159 words
A semiconductor device having a memory cell array region and a peripheral circuit region for driving a cell, the memory cell array region having a plurality of cell transistors, the device comprising: a plurality of buried diffusion layers extending on a semiconductor substrate, the diffusion layers forming bit lines, source regions, and drain regions of the plurality of cell transistors; and a plurality of word lines extending perpendicularly to the plurality of buried diffusion layers, the plurality of word lines forming gate electrodes of the plurality of cell transistors, wherein the gate electrodes of the cell transistors have asymmetrical and polygonal cross-sections; and deposition structures on the gate electrodes of the cell transistors is different from deposition structures on gate electrodes of peripheral circuit transistors formed in the peripheral circuit region; wherein each of the gate electrodes of the cell transistors formed in the memory cell array region have a mirror symmetry with respect to an adjacent gate electrode.
Claim 9
Dependent Claim
22 words
The semiconductor device of claim 4 wherein spacers are formed of an insulating film on the gate electrodes of the cell transistors.
Claim 10
Independent Claim
214 words
A method for fabricating semiconductor devices, comprising: forming a buried diffusion layer as a source/drain region on the surface of a semiconductor substrate; sequentially forming a gate insulating layer, a conductive layer, an etch stop layer, and a first mask layer on the substrate having the buried diffusion layer formed thereon; forming a first photoresist pattern on portions of a memory cell array region of the substrate and entirely on a peripheral circuit region; patterning the first mask layer perpendicularly to the buried diffusion layer in the memory cell array region; forming a second mask layer on the patterned first mask layer in the memory cell array region and on the first mask layer in the peripheral circuit region; forming spacers on the sidewalls of the patterned first mask layer of the memory cell array region by etching back the second mask layer; removing the second mask layer from the peripheral circuit region; removing the first mask layer from the memory cell array and peripheral circuit regions; forming a gate electrode in the memory cell array region by sequentially etching the etch stop layer and the conductive layer using the spacers as a mask; and forming a gate electrode in the peripheral circuit region by etching the etch stop layer and the conductive layer.
Claim 11
Independent Claim
214 words
A method for fabricating semiconductor devices, comprising: forming a buried diffusion layer as a source/drain region on the surface of a semiconductor substrate; sequentially forming a gate insulating layer, a conductive layer, an etch stop layer, and a first mask layer on the substrate having the buried diffusion layer formed thereon; forming a first photoresist pattern on portions of a memory cell array region of the substrate and entirely on a peripheral circuit region; patterning the first mask layer perpendicularly to the buried diffusion layer in the memory cell array region; forming a second mask layer on the patterned first mask layer in the memory cell array region and on the first mask layer in the peripheral circuit region; forming spacers on the sidewalls of the patterned first mask layer of the memory cell array region by etching back the second mask layer; removing the second mask layer from the peripheral circuit region; removing the first mask layer from the memory cell array and peripheral circuit regions; forming a gate electrode in the memory cell array region by sequentially etching the etch stop layer and the conductive layer using the spacers as a mask; and forming a gate electrode in the peripheral circuit region by etching the etch stop layer and the conductive layer.
Claim 12
Dependent Claim
73 words
The method of claim 6 including: forming a second photoresist pattern over the peripheral circuit region before forming the gate electrode in the memory cell array region; removing the second photoresist pattern after forming the gate electrode in the memory cell array region; and forming a third photoresist pattern over the memory cell array region and over portions of the peripheral circuit region before forming the gate electrode in the peripheral circuit region.
Claim 13
Independent Claim
133 words
A method for fabricating semiconductor devices, comprising: forming a buried diffusion layer as a source/drain region on the surface of a semiconductor substrate; sequentially forming a gate insulating layer, a conductive layer, an etch stop layer, and a first mask layer on the substrate having the buried diffusion layer formed thereon; patterning the first mask layer perpendicularly to the buried diffusion layer; forming spacers on the sidewalls of the patterned first mask layer by forming a second mask layer on the resultant structure and etching back the second mask layer; removing the first mask layer; and forming a gate electrode on the conductive layer by sequentially etching the etch stop layer and the conductive layer using the spacers as a mask; wherein the etch stop layer is formed of a reflection blocking material.
Claim 14
Independent Claim
133 words
A method for fabricating semiconductor devices, comprising: forming a buried diffusion layer as a source/drain region on the surface of a semiconductor substrate; sequentially forming a gate insulating layer, a conductive layer, an etch stop layer, and a first mask layer on the substrate having the buried diffusion layer formed thereon; patterning the first mask layer perpendicularly to the buried diffusion layer; forming spacers on the sidewalls of the patterned first mask layer by forming a second mask layer on the resultant structure and etching back the second mask layer; removing the first mask layer; and forming a gate electrode on the conductive layer by sequentially etching the etch stop layer and the conductive layer using the spacers as a mask; wherein the etch stop layer is formed of a reflection blocking material.
Claim 15
Dependent Claim
30 words
The method of claim 8 wherein the first mask layer is formed of a material having a higher etch selectivity than a material used to form the etch stop layer.
Claim 16
Dependent Claim
29 words
The method of claim 8 wherein the second mask layer is formed of a material having a higher etch selectivity than a material used to form the conductive layer.
Claim 17
Independent Claim
198 words
A method for fabricating a semiconductor device having a memory cell array region in which a plurality of cell transistors is formed and a peripheral circuit region which drives a cell, said method comprising: (a) forming a buried diffusion layer as source/drain regions of said cell transistor on the surface of a semiconductor substrate; (b) sequentially forming a gate insulating layer, a conductive layer, an etch stop layer and a first mask layer on the semiconductor substrate having said buried diffusion layer formed thereon; (c) patterning said first mask layer of the memory cell array region perpendicularly to said buried diffusion layer; (d) forming spacers on the sidewalls of said patterned first mask layer by forming a second mask layer on the resultant structure and by etching back said second mask layer; (e) removing said first mask layer; (f) forming a gate electrode of said cell transistor on the conductive layer by sequentially etching said etch stop layer and said conductive layer by use of said spacers as masks; and (g) forming a gate electrode of the peripheral circuit transistor on the conductive layer by patterning said etch stop layer and conductive layer in said peripheral circuit region.
Claim 18
Independent Claim
198 words
A method for fabricating a semiconductor device having a memory cell array region in which a plurality of cell transistors is formed and a peripheral circuit region which drives a cell, said method comprising: (a) forming a buried diffusion layer as source/drain regions of said cell transistor on the surface of a semiconductor substrate; (b) sequentially forming a gate insulating layer, a conductive layer, an etch stop layer and a first mask layer on the semiconductor substrate having said buried diffusion layer formed thereon; (c) patterning said first mask layer of the memory cell array region perpendicularly to said buried diffusion layer; (d) forming spacers on the sidewalls of said patterned first mask layer by forming a second mask layer on the resultant structure and by etching back said second mask layer; (e) removing said first mask layer; (f) forming a gate electrode of said cell transistor on the conductive layer by sequentially etching said etch stop layer and said conductive layer by use of said spacers as masks; and (g) forming a gate electrode of the peripheral circuit transistor on the conductive layer by patterning said etch stop layer and conductive layer in said peripheral circuit region.
Claim 19
Independent Claim
195 words
A method for fabricating a semiconductor device having a memory cell array region in which a plurality of cell transistors is formed and a peripheral circuit region for driving a memory cell, the method comprising: (a) forming a buried diffusion layer as source/drain regions of one of the plurality of cell transistors on a semiconductor substrate; (b) sequentially forming a gate insulating layer, a conductive layer, an etch stop layer, and a first mask layer on the semiconductor substrate; (c) patterning the first mask layer perpendicularly to the buried diffusion layer; (d) forming spacers on the sidewalls of the patterned first mask layer by forming a second mask layer on the resultant structure and etching back the second mask layer; (e) removing the first mask layer; (f) forming a gate electrode of the cell transistor on the conductive layer by sequentially etching the etch stop layer and the conductive layer using the spacers as masks; and (g) forming a gate electrode of a peripheral circuit transistor on the conductive layer by patterning the etch stop layer and conductive layer in the peripheral circuit region; wherein the etch stop layer is formed of an anti-reflection material.
Claim 20
Independent Claim
195 words
A method for fabricating a semiconductor device having a memory cell array region in which a plurality of cell transistors is formed and a peripheral circuit region for driving a memory cell, the method comprising: (a) forming a buried diffusion layer as source/drain regions of one of the plurality of cell transistors on a semiconductor substrate; (b) sequentially forming a gate insulating layer, a conductive layer, an etch stop layer, and a first mask layer on the semiconductor substrate; (c) patterning the first mask layer perpendicularly to the buried diffusion layer; (d) forming spacers on the sidewalls of the patterned first mask layer by forming a second mask layer on the resultant structure and etching back the second mask layer; (e) removing the first mask layer; (f) forming a gate electrode of the cell transistor on the conductive layer by sequentially etching the etch stop layer and the conductive layer using the spacers as masks; and (g) forming a gate electrode of a peripheral circuit transistor on the conductive layer by patterning the etch stop layer and conductive layer in the peripheral circuit region; wherein the etch stop layer is formed of an anti-reflection material.
Claim 21
Dependent Claim
24 words
The method of claim 12 wherein the first mask layer is formed of a material having a higher etch selectivity than the etch layer.
Claim 22
Dependent Claim
24 words
The method of claim 12 wherein the second mask layer is formed of a material having a higher etch selectivity than the conductive layer.
Claim 23
Dependent Claim
22 words
The method of claim 12 wherein patterning the first mask layer comprises removing the first mask layer of the peripheral circuit region.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-03-26 | 2004-09-25 | 2005-03-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-03-26 | 2008-09-25 | 2009-03-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-03-26 | 2012-09-25 | 2013-03-27 | $7700.00 | Window Closed / Lapsed |