US5015601A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a nonvolatile semiconductor device
Assignee: Toshiba Corp
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Filing: 1990-07-18
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Granted: 1991-05-14
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Expires: 2010-07-18
Abstract
Abstract A source diffusion region and a drain diffusion region are formed under an insulation film which is thicker than a gate insulation film and which isolates the adjacent channel regions from each other. The adjacent source and drain diffusion regions are isolated from each other by a trench which extends from the central portion of the thick insulation film to the interior of a semiconductor substrate. The trench is formed in a self-alignment manner with reference to the end portions of the adjacent floating gate electrodes, and the depth of this trench is determined so that the adjacent source and drain diffusion regions can be spaced sufficiently apart from each other. Since the trench reliably prevents punch-through and current leakage to the adjacent element, it is possible to remarkably reduce the cell size. Moreover, the peripheral circuits are not complicated since the functions of the source and drain regions are fixed.
Inventors
- 👤 Kuniyoshi Yoshikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 21:29
CPC Classifications
H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; Y; Y10; Y10S; Y10S148/00; Y10S148/05
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
197 words
A method of manufacturing a nonvolatile semiconductor device, comprising the steps of: forming embedded layers of a second conductivity type in a semiconductor substrate of a first conductivity type; forming a channel region between the embedded layers by ion implantation, and then forming a first gate insulation film on the channel region; forming an insulation film which is thicker than the first gate insulation film and located on the embedded layer; forming a first gate electrode above the channel region such that the first gate electrode is kept in an electrically floating condition by the first gate insulation film, said first gate electrode being formed for each element; forming a trench which extends through the insulation film and the embedded layer and reaches the interior of the semiconductor substrate, thereby dividing the embedded layer into a source region and a drain region; filling the trench with an insulating material, thereby insulating and isolating one element from an adjacent one; forming a second insulation film over the resultant semiconductor structure; and forming a second gate electrode on the first gate electrode, the insulation film, and the trench, so as to electrically connect one element to the adjacent one.
Claim 2
Independent Claim
197 words
A method of manufacturing a nonvolatile semiconductor device, comprising the steps of: forming embedded layers of a second conductivity type in a semiconductor substrate of a first conductivity type; forming a channel region between the embedded layers by ion implantation, and then forming a first gate insulation film on the channel region; forming an insulation film which is thicker than the first gate insulation film and located on the embedded layer; forming a first gate electrode above the channel region such that the first gate electrode is kept in an electrically floating condition by the first gate insulation film, said first gate electrode being formed for each element; forming a trench which extends through the insulation film and the embedded layer and reaches the interior of the semiconductor substrate, thereby dividing the embedded layer into a source region and a drain region; filling the trench with an insulating material, thereby insulating and isolating one element from an adjacent one; forming a second insulation film over the resultant semiconductor structure; and forming a second gate electrode on the first gate electrode, the insulation film, and the trench, so as to electrically connect one element to the adjacent one.
Claim 3
Dependent Claim
26 words
A method according to claim 1, wherein said trench-forming step is carried out by self-aligning end portions of the first gate electrodes of adjacent two elements.
Claim 4
Dependent Claim
24 words
A method according to claim 1, further comprising the step of forming a BPSG film on the whole surface of the resultant semiconductor structure.
References Cited (Backward Citations)
US4455740A
Cited
JPS61214446A
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JPS6288369A
Cited
US4855800A
Cited
JPS6386560A
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JPS63168053A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-05-13 | 1994-11-12 | 1995-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-05-13 | 1998-11-12 | 1999-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-05-13 | 2002-11-12 | 2003-05-14 | $7700.00 | Window Closed / Lapsed |