Low temperature thin film transistor fabrication

Claim 1

In a process of fabricating a low temperature thin film transistor by serial deposition of at least a semiconductor layer in contact with a gate insulation layer, the improvement comprising in combination: providing a substrate of at least one material talen from the group of polycarbonate, polyethylene terephthalate, silicon, quartz and glass, depositing , by a process taken from the group of sputtering, spinning, evaporation and laser ablation at a substrate temperature in the range of about 25 to 150 degrees C., a gate electrode on said substrate, said gate electrode being taken from the group of doped silicon, gold, silver, copper, aluminum, molybdenum, platinum and conducting polymers, an inorganic oxide gate insulation layer on said substrate and over said gate, said gate insulation being of at least one inorganic oxide taken from the group of inorganic oxides including Ta 2 O 3 , V 2 O 3 , Ti O 2 , the ferroelectric insulators Bi 4 Ti 3 O 12 , Ba Mg F 4 , Sr Ti O 3 , and the mixed oxides Sr Bi 2 Ta( 1-x )Nb( x )O 3 , PbZr( x )Ti( 1-x )O 3 , BaZr( x )Ti( 1-x )O 3 , and Ba( x )Sr( 1-x )TiO 3 , an organic semiconductor layer over said inorganic oxide gate insulation layer and, source and drain electrodes on said organic semiconductor layer overlapping said gate and separated by a channel distance, said source and drain electrodes being taken from the group of doped silicon, gold, silver, copper, aluminum, molybdenum, platinum and conducting polymers.