Synchronous dynamic random-access memory

Claim 2

A double data rate synchronous dynamic random-access memory comprising: an address signal line over which an unused column address signal is sent to a byte mask data latch circuit to form a mask signal.

Claim 3

A double data rate synchronous dynamic random-access memory comprising: an address signal line over which an unused column address signal is sent to a byte mask data latch circuit, wherein said column address signal is allocated for a rising edge or a falling edge of a data strobe signal to form a mask signal of a data signal to allow data to be masked on a bit basis during writing.

Claim 4

A double data rate synchronous dynamic random-access memory comprising: an address signal line over which an unused column address signal is sent to a byte mask data latch circuit, wherein said column address signal is allocated for a rising edge or a falling edge of a data strobe signal to form a mask signal of a data signal to allow data to be masked on a bit basis during writing.

Claim 5

The double data rate synchronous dynamic random-access memory according to claim 1 , further comprising a data mask signal line over which a data mask signal is sent to said byte mask data latch circuit to form the mask signal.

Claim 6

The double data rate synchronous dynamic random-access memory according to claim 2 , further comprising a data mask signal line over which a data mask signal is sent to said byte mask data latch circuit to form the mask signal.

Claim 7

The double data rate synchronous dynamic random-access memory according to claim 1 wherein the two unused low-order column address signals are used as data mask signals.

Claim 8

The double data rate synchronous dynamic random-access memory according to claim 2 wherein the two unused low-order column address signals are used as data mask signals.

Claim 9

A double data rate synchronous dynamic random-access memory having a multiple-bank memory cell array driven in synchronization with a first clock, said synchronous dynamic random-access memory comprising: an input/output buffer to or from which data signals of the synchronous dynamic random-access memory are input or output in response to a second clock synchronizing with said first clock; a latch circuit which performs an input/output of the data signals between the input/output buffer and the memory cell array; and a byte mask data latch circuit which allocates an unused column address signal to the latch circuit for use when said data strobe signal rises or falls for outputting a mask signal; wherein said mask signal write-masks the data signals.

Claim 10

A double data rate synchronous dynamic random-access memory having a multiple-bank memory cell array driven in synchronization with a first clock, said synchronous dynamic random-access memory comprising: an input/output buffer to or from which data signals of the synchronous dynamic random-access memory are input or output in response to a second clock synchronizing with said first clock; a latch circuit which performs an input/output of the data signals between the input/output buffer and the memory cell array; and a byte mask data latch circuit which allocates an unused column address signal to the latch circuit for use when said data strobe signal rises or falls for outputting a mask signal; wherein said mask signal write-masks the data signals.

Claim 11

The double data rate synchronous dynamic random-access memory according to claim 7 wherein said byte mask data latch circuit comprises a first latch circuit and a second latch circuit, said first latch circuit latching the data mask signal supplied from an external of the memory in response to a data strobe signal and the second latch circuit latching the unused column address signal in response to a inverse of data strobe signal.

Claim 12

The double data rate synchronous dynamic random-access memory according to claim 7 wherein said byte mask data latch circuit comprises a first latch circuit and a second latch circuit, said first and second latch circuits latching the two unused column address signals in response to the data strobe signal and an inverse thereof.

Claim 13

The double data rate synchronous dynamic random-access memory according to claim 9 wherein said byte mask data latch circuit outputs logical products of said two unused column address signals and said data mask signal and, at the same time, latches the logical products.