Patent US6204715B1 successfully refreshed from Google Patents.
US6204715B1
Expired / Lapsed
US
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Signal amplifying circuit
Assignee: Motors Liquidation Co
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Filing: 1999-02-26
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Granted: 2001-03-20
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Expires: 2019-02-26
Abstract
Abstract Circuitry for amplifying a single-ended analog sensor output includes a field effect transistor (FET) having a gate connected to a first end of a capacitor, the second opposite end of which is connectable to the sensor output. The gate of the FET is also connected to a first end of a resistor and to a cathode of a diode. The anode of the diode, the opposite end of the resistor and the drain of the FET are connectable to a ground reference, and the source of the FET defines an amplifier output that is connectable to a constant current source. The capacitor, resistor and diode are operable to bias the FET to thereby prevent clipping of the output signal at the amplifier output. A high-pass filter is also provided at the second end of the capacitor, and a number of diodes are preferably included for providing for amplifier input protection, electrostatic discharge protection and output DC overvoltage protection. When the amplifying circuit of the present invention is implemented integral with a single-ended, case grounded sensor configuration, only one wire per sensor is required.
Inventors
- 👤 Mark C. Sellnau
- 👤 Raymond A. Tidrow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 16:20
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/50; H03F3/505
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
159 words
A signal amplifying circuit comprising: a first capacitor having a first end adapted for connection to a signal source and a second opposite end; a field effect transistor (FET) having a gate connected to said second end of said first capacitor, one of a drain and a source adapted for connection to a reference potential and an opposite one of said drain and a source defining a circuit output; and a first diode having a cathode connected to said gate and an anode connected to said one of a drain and a source adapted for connection to a reference potential, said first capacitor and said first diode establishing a positive bias at said gate of said FET with respect to said reference potential when an input signal at said first end of said first capacitor is negative with respect to said reference potential to thereby prevent clipping of an output signal provided by said FET at said circuit output.
Claim 2
Dependent Claim
159 words
A signal amplifying circuit comprising: a first capacitor having a first end adapted for connection to a signal source and a second opposite end; a field effect transistor (FET) having a gate connected to said second end of said first capacitor, one of a drain and a source adapted for connection to a reference potential and an opposite one of said drain and a source defining a circuit output; and a first diode having a cathode connected to said gate and an anode connected to said one of a drain and a source adapted for connection to a reference potential, said first capacitor and said first diode establishing a positive bias at said gate of said FET with respect to said reference potential when an input signal at said first end of said first capacitor is negative with respect to said reference potential to thereby prevent clipping of an output signal provided by said FET at said circuit output.
Claim 3
Dependent Claim
53 words
The signal amplifier circuit of claim 1 further including a second capacitor having a first end connected to said first end of said first capacitor and a second opposite end connected to said anode of said first diode, said second capacitor forming a charge attenuator and determining a gain of said amplifier circuit.
Claim 4
Dependent Claim
50 words
The signal amplifier circuit of claim 2 further including a second resistor having a first end connected to said first end of said first capacitor and a second opposite end connected to said anode of said first diode, said second resistor and said second capacitor forming a high pass filter.
Claim 5
Dependent Claim
67 words
The signal amplifier of claim 3 further including: a second diode having an anode connected to said gate of said FET and a cathode connected to said circuit output; and a third diode having an anode connected to said second end of said first resistor and a cathode connected to said circuit output, said first, second and third diodes providing for amplifier input and electrostatic discharge protection.
Claim 6
Dependent Claim
18 words
The signal amplifier of claim 1 wherein said FET is a metal oxide semiconductor field effect transistor (MOSFET).
Claim 7
Dependent Claim
15 words
The signal amplifier of claim 5 wherein said MOSFET is a p-channel enhancement mode MOSFET.
Claim 8
Dependent Claim
44 words
The signal amplifier of claim 1 further including a first resistor having a first end connected to said cathode and a second end connected to said anode of said first diode, said first resistor dissipating said positive bias on said gate of said FET.
Claim 9
Dependent Claim
158 words
A signal amplifying system comprising: a sensor responsive to excitation thereof to produce a sensor signal at a sensor output thereof; a signal amplifier having a first field effect transistor (FET) defining a gate coupled to said sensor output, one of a drain and a source connected to a reference potential and an opposite one of said drain and a source defining an amplifier output; a current source connected to said amplifier output and supplying a constant current thereto; a first diode connected between said gate of said first FET and said reference potential; and a capacitor connected between said sensor output and said gate of said first FET, said first diode and said first capacitor establishing a positive bias at said gate of said first FET with respect to said reference potential when said sensor signal is negative with respect to said reference potential to thereby prevent clipping of an output signal provided at said amplifier output.
Claim 10
Dependent Claim
158 words
A signal amplifying system comprising: a sensor responsive to excitation thereof to produce a sensor signal at a sensor output thereof; a signal amplifier having a first field effect transistor (FET) defining a gate coupled to said sensor output, one of a drain and a source connected to a reference potential and an opposite one of said drain and a source defining an amplifier output; a current source connected to said amplifier output and supplying a constant current thereto; a first diode connected between said gate of said first FET and said reference potential; and a capacitor connected between said sensor output and said gate of said first FET, said first diode and said first capacitor establishing a positive bias at said gate of said first FET with respect to said reference potential when said sensor signal is negative with respect to said reference potential to thereby prevent clipping of an output signal provided at said amplifier output.
Claim 11
Dependent Claim
26 words
The signal amplifying system of claim 8 wherein said sensor is a high impedance sensor operable to produce a single-ended output signal at said sensor output.
Claim 12
Dependent Claim
14 words
The signal amplifying system of claim 9 wherein said sensor is a piezoelectric sensor.
Claim 13
Dependent Claim
26 words
The signal amplifying system of claim 10 wherein said sensor is a pressure sensor operable to sense pressure in a cylinder of an internal combustion engine.
Claim 14
Dependent Claim
24 words
The signal amplifying system of claim 8 wherein said current source forms part of a circuit separate from said sensor and said amplifier circuit.
Claim 15
Dependent Claim
18 words
The signal amplifying system of claim 8 further including means for limiting load current through said first FET.
Claim 16
Dependent Claim
75 words
The signal amplifying system of claim 13 wherein said means for limiting load current through said first FET includes a second field effect transistor (FET) disposed between said amplifier output and said opposite one of said drain and source of said first FET, said second FET having a drain connected to said amplifier output and a gate and source each connected to said opposite one of said drain and a source of said first FET.
Claim 17
Dependent Claim
85 words
The signal amplifying system of claim 14 further including: a second diode having an anode connected to said gate of said first FET and a cathode connected to said source and gate of said second FET; a third diode having an anode connected to said reference potential and a cathode connected to said source and gate of said second FET; and a fourth diode having an anode connected to said source and gate of said second FET and a cathode connected to said amplifier output.
Claim 18
Dependent Claim
51 words
The signal amplifying system of claim 14 further including: a second diode having an anode connected to said gate of said first FET and a cathode connected to said amplifier output; and a third diode having an anode connected to said reference potential and a cathode connected to said amplifier output.
Claim 19
Dependent Claim
18 words
The signal amplifying system of claim 14 wherein said second FET is a junction field effect transistor (JFET).
Claim 20
Dependent Claim
66 words
The signal amplifying system of claim 14 further including: a second capacitor having a first end connected to said sensor output and a second opposite end connected to said reference potential; and a resistor having a first end connected to said first end of said capacitor and a second opposite end connected to said reference potential, said resistor and said capacitor forming a high pass filter.
Claim 21
Dependent Claim
22 words
The signal amplifying system of claim 18 wherein said first FET is a metal oxide semiconductor p-channel enhancement mode field effect transistor.
Claim 22
Dependent Claim
35 words
The signal amplifying system of claim 8 further including a resistor connected between said gate of said FET and said reference potential, said resistor dissipating said positive bias on said gate of said first FET.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-03-19 | 2004-09-18 | 2005-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-03-19 | 2008-09-18 | 2009-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-03-19 | 2012-09-18 | 2013-03-20 | $7700.00 | Window Closed / Lapsed |