US6204559B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ball grid assembly type semiconductor package having improved chip edge support to prevent chip cracking
Assignee: Advanced Semiconductor Engineering Inc
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Filing: 1999-11-22
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Granted: 2001-03-20
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Expires: 2019-11-22
Abstract
Abstract This invention moves at least one outer via outwardly to a location under the edge of the chip so as to form an offset via. Since the via is made of copper, the offset via provides sufficient supporting strength for the chip edge during molding process. Further, this invention also disposes a copper mesh on the substrate at the area without vias and traces so as to enhance the substrate strength for supporting the chip. According to another aspect of this invention, dummy via holes are provided for the substrate at the area under the chip edge for supporting the chip. Since the copper mesh, offset via, the dummy via hole are made of copper having sufficient supporting strength for the chip, the crack problem during molding process can be eliminated.
Inventors
- 👤 Chun Hung Lin
- 👤 Yire Zine Lee
- 👤 Su Tao
- 👤 Jian Wen Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 08:02
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/688; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W74/117; H10W90/00; H10W90/701; H10W72/00; H10W72/071; H10W72/075; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/951; H10W90/731; H10W90/734; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
219 words
A semiconductor package comprising: a thin substrate having a dielectric layer, the thin substrate having a pair of longitudinal edges and a pair of lateral edges, the dielectric layer having an upper surface and lower surface; a plurality of bonding pads and traces disposed on the upper surface of the dielectric layer, the bonding pads locating along the longitudinal edges of the thin substrate and electrically connecting to the corresponding traces; a plurality of solder ball pads disposed at the lower surface of the dielectric layer; a plurality of vias, each connecting the solder ball pad to the corresponding bonding pad through the trace; a plurality of solder balls mounted on the solder ball pads for connecting to external circuits; a chip attached on the thin substrate, the chip having a pair of longitudinal edges and a pair of lateral edges, the chip having a plurality of chip pads electrically connected to the corresponding bonding pads, and a package body encapsulating the chip and the upper surface of the thin substrate; wherein the area surrounded by the solder balls is smaller than the area of the chip, at least one via is offset disposed under the lateral edge of the chip so as to be closer to the lateral edge, relative to adjacently arranged vias, for supporting the chip.
Claim 2
Dependent Claim
219 words
A semiconductor package comprising: a thin substrate having a dielectric layer, the thin substrate having a pair of longitudinal edges and a pair of lateral edges, the dielectric layer having an upper surface and lower surface; a plurality of bonding pads and traces disposed on the upper surface of the dielectric layer, the bonding pads locating along the longitudinal edges of the thin substrate and electrically connecting to the corresponding traces; a plurality of solder ball pads disposed at the lower surface of the dielectric layer; a plurality of vias, each connecting the solder ball pad to the corresponding bonding pad through the trace; a plurality of solder balls mounted on the solder ball pads for connecting to external circuits; a chip attached on the thin substrate, the chip having a pair of longitudinal edges and a pair of lateral edges, the chip having a plurality of chip pads electrically connected to the corresponding bonding pads, and a package body encapsulating the chip and the upper surface of the thin substrate; wherein the area surrounded by the solder balls is smaller than the area of the chip, at least one via is offset disposed under the lateral edge of the chip so as to be closer to the lateral edge, relative to adjacently arranged vias, for supporting the chip.
Claim 3
Dependent Claim
20 words
The semiconductor package as claimed in claim 1 , wherein the offset via is connected to the outmost bonding pad.
Claim 4
Dependent Claim
44 words
The semiconductor package as claimed in claim 1 , further comprising a copper mesh disposed under the lateral edge of the chip and on the substrate at the area without vias and traces so as to enhance the substrate strength for supporting the chip.
Claim 5
Dependent Claim
21 words
The semiconductor package as claimed in claim 1 , wherein the thin substrate has a thickness no more than 0.36 mm.
Claim 6
Dependent Claim
16 words
The semiconductor package as claimed in claim 1 , wherein outer vias form a staggered configuration.
Claim 7
Dependent Claim
191 words
A semiconductor package comprising: a thin substrate having a dielectric layer, the thin substrate having a pair of longitudinal edges and a pair of lateral edges, the dielectric layer having an upper surface and lower surface; a plurality of bonding pads and traces disposed on the upper surface of the dielectric layer, the bonding pads locating along the longitudinal edges of the thin substrate and electrically connecting to the corresponding traces; a plurality of solder ball pads disposed at the lower surface of the dielectric layer; a plurality of vias, each connecting the solder ball pad to the corresponding bonding pad through the trace; a plurality of solder balls mounted on the solder ball pads for connecting to external circuits; a chip attached on the thin substrate, the chip having a pair of longitudinal edges and a pair of lateral edges, the chip having a plurality of chip pads electrically connected to the corresponding bonding pads, a package body encapsulating the chip and the upper surface of the thin substrate; and at least one dummy via disposed at the trace under the lateral edge of the chip for supporting the chip.
Claim 8
Dependent Claim
191 words
A semiconductor package comprising: a thin substrate having a dielectric layer, the thin substrate having a pair of longitudinal edges and a pair of lateral edges, the dielectric layer having an upper surface and lower surface; a plurality of bonding pads and traces disposed on the upper surface of the dielectric layer, the bonding pads locating along the longitudinal edges of the thin substrate and electrically connecting to the corresponding traces; a plurality of solder ball pads disposed at the lower surface of the dielectric layer; a plurality of vias, each connecting the solder ball pad to the corresponding bonding pad through the trace; a plurality of solder balls mounted on the solder ball pads for connecting to external circuits; a chip attached on the thin substrate, the chip having a pair of longitudinal edges and a pair of lateral edges, the chip having a plurality of chip pads electrically connected to the corresponding bonding pads, a package body encapsulating the chip and the upper surface of the thin substrate; and at least one dummy via disposed at the trace under the lateral edge of the chip for supporting the chip.
Claim 9
Dependent Claim
20 words
The semiconductor package as claimed in claim 6 , wherein the dummy via is connected to the outmost bonding pad.
Claim 10
Dependent Claim
44 words
The semiconductor package as claimed in claim 6 , further comprising a copper mesh disposed under the lateral edge of the chip and on the substrate at the area without vias and traces so as to enhance the substrate strength for supporting the chip.
Claim 11
Dependent Claim
21 words
The semiconductor package as claimed in claim 6 , wherein the thin substrate has a thickness no more than 0.36 mm.
Claim 12
Dependent Claim
33 words
The semiconductor package of claim 1 , wherein said at least one offset via is closer to the lateral edge than an adjacent row of vias extending generally parallel to said lateral edge.
References Cited (Backward Citations)
US5640048A
Cited
US5581122A
Cited
US5909054A
Cited
US5640047A
Cited
US5874784A
Cited
US5945741A
Cited
US5959356A
Cited
US5796589A
Cited
US5962917A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-03-19 | 2004-09-18 | 2005-03-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-03-19 | 2008-09-18 | 2009-03-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-03-19 | 2012-09-18 | 2013-03-20 | $7700.00 | Window Closed / Lapsed |