Patent US6199144B1 successfully refreshed from Google Patents.
US6199144B1
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Method and apparatus for transferring data in a computer system
Assignee: INSTITUTE FOR DEVELOPMENT OF EMERGING ARCHITECTURES C/O HEWLETT-PACKARD Co LLC
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Filing: 1997-12-31
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Granted: 2001-03-06
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Expires: 2017-12-31
Abstract
Abstract A method and apparatus for transferring data from a first memory location to a second memory location in a computer system. A load instruction is executed, and, in response, data is transferred from a first memory location to a second memory location during a single bus transaction. During the same bus transaction, a request is made to invalidate a copy of the data that is stored in a third memory location if the load instruction indicates to do so.
Inventors
- 👤 Judge K. Arora
- 👤 William R. Bryg
- 👤 Stephen G. Burger
- 👤 Gary N. Hammond
- 👤 Michael L. Ziegler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:52
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0833
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
105 words
A method of manipulating data in a computer system, the method comprising: executing a load instruction; requesting ownership of a bus; transferring a first data value from a first memory location to a second memory location via the bus during a single bus transaction in response to executing the load instruction; and requesting invalidation, during the single bus transaction, of a copy of the first data value stored in a third memory location, thereby allowing the first data value to be placed in an exclusive state in the second memory location without re-requesting ownership of the bus, if the load instruction indicates to do so.
Claim 2
Independent Claim
105 words
A method of manipulating data in a computer system, the method comprising: executing a load instruction; requesting ownership of a bus; transferring a first data value from a first memory location to a second memory location via the bus during a single bus transaction in response to executing the load instruction; and requesting invalidation, during the single bus transaction, of a copy of the first data value stored in a third memory location, thereby allowing the first data value to be placed in an exclusive state in the second memory location without re-requesting ownership of the bus, if the load instruction indicates to do so.
Claim 3
Dependent Claim
30 words
The method of claim 1 , further comprising: modifying the first data value to create a modified data value; and storing the modified data value in the second memory location.
Claim 4
Dependent Claim
38 words
The method of claim 1 , further comprising transferring a second data value from a fourth memory location that is in the same page as the first memory location to a fifth memory location in a shared state.
Claim 5
Dependent Claim
48 words
The method of claim 3 , wherein the load instruction indicates to request the invalidation if the load instruction is an exclusive load instruction, and the load instruction indicates to transfer the second data value in a shared state if the load instruction is a shared load instruction.
Claim 6
Dependent Claim
24 words
The method of claim 1 , wherein the load instruction indicates to request the invalidation if the load instruction is an exclusive load instruction.
Claim 7
Dependent Claim
40 words
The method of claim 1 , wherein transferring the first data value includes transferring the first data value from a first cache to a second cache, the second cache being a local cache in a processor of the computer system.
Claim 8
Dependent Claim
74 words
The method of claim 1 , wherein transferring the first data value includes transferring the first data value from a first cache to a second cache, the second cache being a first local cache in a first processor of a multi-processor computer system, and further comprising invalidating, in response to requesting invalidation, a copy of the first data value stored in a second local cache in a second processor of the multi-processor computer system.
Claim 9
Dependent Claim
92 words
The method of claim 3 , wherein transferring the first data value includes transferring the first data value from a first cache to a second cache, the second cache being a first local cache in a first processor of a multi-processor computer system, transferring the second data value transfers the second data value from the first cache to the second cache, and further comprising invalidating, in response to requesting invalidation, a copy of the first data value stored in a second local cache in a second processor of the multi-processor computer system.
Claim 10
Dependent Claim
67 words
The method of claim 1 , wherein transferring the first data value includes transferring the first data value from a first cache to a second cache, the second cache being a first local cache in a first processor of the computer system, and further comprising invalidating, in response to requesting invalidation, a copy of the first data value stored in a bus master of the computer system.
Claim 11
Independent Claim
100 words
A method of manipulating data in a computer system that includes a first processor, the method comprising: executing an exclusive load instruction that instructs the first processor to, during a single bus transaction, cause a first data value to be transferred from a shared memory location to a first local cache of the first processor in an exclusive state, thereby circumventing placing the first data value in a shared state in the first local cache; and executing a store instruction that instructs the first processor to store a modified version of the first data value in the first local cache.
Claim 12
Independent Claim
100 words
A method of manipulating data in a computer system that includes a first processor, the method comprising: executing an exclusive load instruction that instructs the first processor to, during a single bus transaction, cause a first data value to be transferred from a shared memory location to a first local cache of the first processor in an exclusive state, thereby circumventing placing the first data value in a shared state in the first local cache; and executing a store instruction that instructs the first processor to store a modified version of the first data value in the first local cache.
Claim 13
Dependent Claim
51 words
The method of claim 10 , further comprising executing a shared load instruction that instructs the first processor to cause a second data value from a memory location that is in the same page as the shared memory location to be transferred to the first local cache in a shared state.
Claim 14
Dependent Claim
48 words
The method of claim 10 , wherein executing an exclusive load instruction instructs the first processor to, during the single bus transaction, cause a copy of the first data value stored in a second local cache in a second processor of a multi-processor computer system to be invalidated.
Claim 15
Dependent Claim
42 words
The method of claim 10 , wherein executing an exclusive load instruction instructs the first processor to, during the single bus transaction, cause a copy of the first data value stored in a bus master of the computer system to be invalidated.
Claim 16
Dependent Claim
100 words
A processor having an instruction set associated therewith, the instruction set including a first load instruction that, when executed by the processor, causes the processor to: request ownership of a bus; transfer a first data value from a first memory location to a second memory location, via the bus, during a single bus transaction; and request, during the single bus transaction, invalidation of a copy of the first data value stored in a third memory location, thereby allowing the first data value to be placed in an exclusive state in the second memory location without re-requesting ownership of the bus.
Claim 17
Dependent Claim
100 words
A processor having an instruction set associated therewith, the instruction set including a first load instruction that, when executed by the processor, causes the processor to: request ownership of a bus; transfer a first data value from a first memory location to a second memory location, via the bus, during a single bus transaction; and request, during the single bus transaction, invalidation of a copy of the first data value stored in a third memory location, thereby allowing the first data value to be placed in an exclusive state in the second memory location without re-requesting ownership of the bus.
Claim 18
Dependent Claim
56 words
The processor of claim 14 , wherein the instruction set further includes a second load instruction that, when executed by the processor, causes the processor to transfer a second data value to a fifth memory location in a shared state from a fourth memory location that is in the same page as the first memory location.
Claim 19
Dependent Claim
21 words
The processor of claim 15 , wherein the second and fifth memory locations are a first local cache in the processor.
Claim 20
Dependent Claim
28 words
The processor of claim 14 , wherein the first memory location is a shared cache and the second memory location is a first local cache in the processor.
Claim 21
Dependent Claim
41 words
The processor of claim 14 , wherein the first memory location is a shared cache, the second memory location is a first local cache in the processor, and the third memory location is a second local cache in a second processor.
Claim 22
Dependent Claim
51 words
The processor of claim 14 , wherein the second memory location is a first local cache in the processor and the request for the invalidation causes a copy of the first data value stored in a second local cache in a second processor of a multi-processor computer system to be invalidated.
Claim 23
Dependent Claim
45 words
The processor of claim 14 , wherein the second memory location is a first local cache in the processor and the request for the invalidation causes a copy of the first data value stored in a bus master of a computer system to be invalidated.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-03-05 | 2004-09-04 | 2005-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-03-05 | 2008-09-04 | 2009-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-03-05 | 2012-09-04 | 2013-03-06 | $7700.00 | Window Closed / Lapsed |