Apparatus and method of handling race conditions in mesi-based multiprocessor system with private caches

Claim 3

The method of claim 1 further comprising the step of: updating a main memory with the data written to the cache line by the first processor.

Claim 4

The method of claim 1 wherein the first request is initiated in a first clock cycle of the MP system and the second request is initiated in a second clock cycle.

Claim 5

The method of claim 1 further comprising the step, prior to step (d), of: detecting, by the second processor, the race condition.

Claim 7

A MESI-based multiprocessor (MP) computer system for handling race conditions comprising: a pipelined bus; a first processor coupled to said pipelined bus, said first processor having a first cache; a second processor coupled to said pipelined bus, said second processor having a second cache; a first memory controller for controlling said first cache; a second memory controller coupled to said first memory controller via said pipelined bus, said second memory controller for controlling said second cache, said first and said second memory controllers determining an existing state of a cache line; a first logic coupled to said first memory controller for writing to said cache line and changing said existing state of said cache line to a modified state if said existing state of said cache line is an Exclusive state; a second logic coupled to said first memory controller for performing a Bus-Read-Invalidate operation if said existing state of said cache line is an Invalid state and allowing an invalidation request corresponding to said first processor to complete if said existing state of said cache line is a Shared state and said first processor and said second processor both initiate Bus-Write-Invalidate operations; a third logic coupled to said first processor for setting said cache line to said Exclusive state, updating data to said cache line, and setting said cache line to said Modified state; a fourth logic coupled to said second processor for receiving a second cache line, updating said second cache line, setting said second cache line to said Exclusive state, writing said data to said second cache line in said Exclusive state, and setting said second cache line to said Modified state.

Claim 8

A MESI-based multiprocessor (MP) computer system for handling race conditions comprising: a pipelined bus; a first processor coupled to said pipelined bus, said first processor having a first cache; a second processor coupled to said pipelined bus, said second processor having a second cache; a first memory controller for controlling said first cache; a second memory controller coupled to said first memory controller via said pipelined bus, said second memory controller for controlling said second cache, said first and said second memory controllers determining an existing state of a cache line; a first logic coupled to said first memory controller for writing to said cache line and changing said existing state of said cache line to a modified state if said existing state of said cache line is an Exclusive state; a second logic coupled to said first memory controller for performing a Bus-Read-Invalidate operation if said existing state of said cache line is an Invalid state and allowing an invalidation request corresponding to said first processor to complete if said existing state of said cache line is a Shared state and said first processor and said second processor both initiate Bus-Write-Invalidate operations; a third logic coupled to said first processor for setting said cache line to said Exclusive state, updating data to said cache line, and setting said cache line to said Modified state; a fourth logic coupled to said second processor for receiving a second cache line, updating said second cache line, setting said second cache line to said Exclusive state, writing said data to said second cache line in said Exclusive state, and setting said second cache line to said Modified state.

Claim 9

The MP computer system of claim 6, wherein said second processor belongs to a different bus cluster.

Claim 10

The MP computer system of claim 7, wherein said first processor and said second processor assert a snoop response and access a system interconnect network coupling said first processor to said second processor to allow a first bus-write-invalidation operation to complete and wherein said first processor sets said cache line to said Exclusive state, updates said cache line in said Exclusive state, and updates said cache line to said Modified state.

Claim 11

The MP computer system of claim 8, wherein said second processor invalidates said cache line associated with said first processor, receives a third cache line, sets said third cache line to said Exclusive state, updates said third cache line, and sets said third cache line to said Modified state.

Claim 12

The MP computer system of claim 6 wherein said first and second caches comprise of write-through caches and all snooping caches are invalidated if said cache line is in said Invalid state and wherein said second memory controller performs a partial write operation, invalidate all snooping caches, sets said cache line to said Exclusive state, and updates said cache line if said cache line is in said Shared state.

Claim 13

The MP computer system of claim 6 further comprising a third processor coupled to said second processor via said pipelined bus, said third processor generating another invalidation request.

Claim 14

The MP computer system of claim 11 further comprising a fifth logic coupled to said third processor for getting ownership of said cache line, wherein said third processor updates a fourth cache line, sets said fourth cache line to said Exclusive state, writes data to said fourth cache line and sets said fourth cache line to said Modified state.

Claim 15

The MP computer system claim 6 further comprising logic to issue a read-invalidation request following a first bus-write-invalidation operation.

Claim 16

A MESI-based multiprocessor (MP) computer system having a plurality of processors coupled to a pipeline system bus, each processor having internal cached memory means, an apparatus for handling race conditions wherein a first processor means and a second processor of said plurality of processors both write to a particular cache line, said apparatus comprising: a first controller means coupled to said first cached memory means for controlling said first cached memory means; a second controller means coupled to said first controller means for controlling a second cached memory means; means for writing to said cache line such that said cache line is in a Modified state; means for performing a Bus-Read-Invalidate operation if said cache line is in an Invalid state; means for allowing an invalidation request corresponding to said first processor to complete if said cache line is in a Shared state and said first processor and said second processor both initiate Bus-Write-Invalidate operations; means for setting said cache line to an Exclusive state, updating data to said cache line, and setting said cache line to said Modified state; means for receiving a second cache line, updating said second cache line, setting said second cache line to said Exclusive state, writing said data to said second cache line, and setting said second cache line to said Modified state.

Claim 17

A MESI-based multiprocessor (MP) computer system having a plurality of processors coupled to a pipeline system bus, each processor having internal cached memory means, an apparatus for handling race conditions wherein a first processor means and a second processor of said plurality of processors both write to a particular cache line, said apparatus comprising: a first controller means coupled to said first cached memory means for controlling said first cached memory means; a second controller means coupled to said first controller means for controlling a second cached memory means; means for writing to said cache line such that said cache line is in a Modified state; means for performing a Bus-Read-Invalidate operation if said cache line is in an Invalid state; means for allowing an invalidation request corresponding to said first processor to complete if said cache line is in a Shared state and said first processor and said second processor both initiate Bus-Write-Invalidate operations; means for setting said cache line to an Exclusive state, updating data to said cache line, and setting said cache line to said Modified state; means for receiving a second cache line, updating said second cache line, setting said second cache line to said Exclusive state, writing said data to said second cache line, and setting said second cache line to said Modified state.

Claim 18

The MP computer system of claim 14, wherein said second processor is coupled to a different bus cluster.

Claim 19

The MP computer system of claim 15, wherein said first processor and said second processor assert a snoop response and access a system interconnect network to allow a first bus-write-invalidation operation to complete and wherein said first processor sets said cache line to said Exclusive state, updates data in said cache line in said Exclusive state, and changes said cache line to said Modified state.

Claim 20

The MP computer system of claim 16, wherein said second processor invalidates said cache line associated with said first processor, receives a third cache line, sets said third cache line to said Exclusive state, updates data in said third cache line, and changes said third cache line to said Modified state.

Claim 21

The MP computer system of claim 14 wherein said cached memory means include write-through cached memory means.

Claim 22

The MP computer system of claim 18, wherein snooping caches are invalidated if said cache line is in said Invalid state and wherein said second controller means performs a partial write operation, invalidates all snooping caches, sets said cache line to said Exclusive state, and updates data in said cache line if said cache line is in said Shared state.

Claim 23

The MP computer system of claim 14 further comprising a third processor coupled to said second processor via said pipelined system bus for generating another invalidation request.

Claim 24

The MP computer system of claim 20 further comprising means for getting ownership of said cache line, wherein said third processor receives a third cache line, sets said third cache line to said Exclusive state, updates data in said third cache line and changes said third cache line to said Modified state.

Claim 25

The MP computer system of claim 14 further comprising means for issuing a read-invalidation request so that said cache line is set to said Invalid state following said first bus-write-invalidation operation.