Patent US6198488B1 successfully refreshed from Google Patents.
US6198488B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transform, lighting and rasterization system embodied on a single semiconductor platform
Assignee: Nvidia Corp
•
Filing: 1999-12-06
•
Granted: 2001-03-06
•
Expires: 2019-12-06
Abstract
Abstract A graphics pipeline system is provided for graphics processing. Such system includes a transform module adapted for being coupled to a vertex attribute buffer for receiving vertex data. The transform module serves to transform the vertex data from object space to screen space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the vertex data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the vertex data received from the lighting module.
Inventors
- 👤 John Erik Lindholm
- 👤 Simon Moy
- 👤 Kevin Dawallu
- 👤 Mingjian Yang
- 👤 John Montrym
- 👤 David B. Kirk
- 👤 Paolo E. Sabella
- 👤 Matthew N. Papakipos
- 👤 Douglas A. Voorhies
- 👤 Nicholas J. Foskett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 16:34
CPC Classifications
G; G06; G06T; G06T11/00; G06T11/40; G06T15/00; G06T15/005; G06T15/04; G06T15/50; G06T15/503; G06T15/506
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
144 words
A graphics pipeline system for graphics processing, comprising: (a) a transform module adapted for being coupled to a buffer to receive vertex data therefrom, the transform module being positioned on a single semiconductor platform for transforming the vertex data from object space to screen space; (b) a lighting module coupled to the transform module and positioned on the same single semiconductor platform as the transform module for performing lighting operations on the vertex data received from the transform module; and (c) a rasterizer coupled to the lighting module and positioned on the same single semiconductor platform as the transform module and lighting module for rendering the vertex data received from the lighting module; (d) wherein at least one of the transform module and the lighting module includes a sequencer for executing multiple threads of operation in parallel through a plurality of logic units thereof.
Claim 2
Dependent Claim
144 words
A graphics pipeline system for graphics processing, comprising: (a) a transform module adapted for being coupled to a buffer to receive vertex data therefrom, the transform module being positioned on a single semiconductor platform for transforming the vertex data from object space to screen space; (b) a lighting module coupled to the transform module and positioned on the same single semiconductor platform as the transform module for performing lighting operations on the vertex data received from the transform module; and (c) a rasterizer coupled to the lighting module and positioned on the same single semiconductor platform as the transform module and lighting module for rendering the vertex data received from the lighting module; (d) wherein at least one of the transform module and the lighting module includes a sequencer for executing multiple threads of operation in parallel through a plurality of logic units thereof.
Claim 3
Dependent Claim
223 words
The system as recited in claim 1 , wherein the lighting module includes: (a) a plurality of input buffers adapted for receiving the vertex data; (b) a multiplication logic unit having a first input coupled to an output of one of the input buffers and a second input coupled to an output of one of the input buffers; (c) an arithmetic logic unit having a first input coupled to an output of one of the input buffers and a second input coupled to an output of the multiplication logic unit; (d) a first register unit having an input coupled to the output of the arithmetic logic unit and an output coupled to the first input of the arithmetic logic unit; (e) a second register unit having an input coupled to the output of the arithmetic logic unit and an output coupled to the first input and the second input of the multiplication logic unit; (f) a lighting logic unit having a first input coupled to the output of the arithmetic logic unit, a second input coupled to the output of one of the input buffers, and an output coupled to the first input of the multiplication logic unit; and (g) a memory coupled to at least one of the inputs of the multiplication logic unit and the output of the arithmetic logic unit.
Claim 4
Dependent Claim
29 words
The system as recited in claim 2 , wherein an output of one of the input buffers is coupled to an output of the lighting module via a delay.
Claim 5
Dependent Claim
39 words
The system as recited in claim 3 , wherein the output of the arithmetic logic unit and an output of one of the input buffers are coupled to the output of the lighting module by way of a multiplexer.
Claim 6
Dependent Claim
26 words
The system as recited in claim 2 , wherein the output of the multiplication logic unit has a feedback loop coupled to the second input thereof.
Claim 7
Dependent Claim
31 words
The system as recited in claim 2 , wherein the second input of the lighting logic unit is coupled to an output of one of the input buffers via a delay.
Claim 8
Dependent Claim
33 words
The system as recited in claim 2 , wherein the output of the lighting logic unit is coupled to the first input of the multiplication logic unit via a first-in first-out register unit.
Claim 9
Dependent Claim
41 words
The system as recited in claim 2 , wherein the output of the lighting logic unit is coupled to the first input of the multiplication logic unit via a conversion module adapted for converting scalar vertex data to vector vertex data.
Claim 10
Dependent Claim
154 words
The system as recited in claim 1 , wherein the transform module includes: (a) an input buffer adapted for receiving vertex data; (b) a multiplication logic unit having a first input coupled to an output of the input buffer; (c) an arithmetic logic unit having a first input coupled to an output of the multiplication logic unit; (d) a register unit having an input coupled to an output of the arithmetic logic unit; (e) an inverse logic unit including an input coupled to the output of the arithmetic logic unit or the register unit for performing an inverse or an inverse square root operation; (f) a conversion module coupled between an output of the inverse logic unit and a second input of the multiplication logic unit, the conversion module adapted to convert scalar vertex data to vector vertex data; and (g) a memory coupled to the multiplication logic unit and the arithmetic logic unit.
Claim 11
Dependent Claim
22 words
The system as recited in claim 9 , wherein the memory is coupled to the second input of the multiplication logic unit.
Claim 12
Dependent Claim
24 words
The system as recited in claim 9 , wherein the memory has a write terminal coupled to the output of the arithmetic logic unit.
Claim 13
Dependent Claim
26 words
The system as recited in claim 9 , wherein the output of the multiplication logic unit has a feedback loop coupled to the first input thereof.
Claim 14
Dependent Claim
26 words
The system as recited in claim 9 , wherein the output of the register unit is coupled to the first input of the multiplication logic unit.
Claim 15
Dependent Claim
26 words
The system as recited in claim 13 , wherein the output of the register unit is coupled to the second input of the multiplication logic unit.
Claim 16
Dependent Claim
26 words
The system as recited in claim 9 , wherein the output of the arithmetic logic unit has a feedback loop connected to the second input thereof.
Claim 17
Dependent Claim
17 words
The system as recited in claim 15 , wherein the feedback loop has a delay coupled thereto.
Claim 18
Dependent Claim
16 words
The system as recited in claim 1 , wherein the rasterizer operates in homogeneous clip space.
Claim 19
Dependent Claim
53 words
The system as recited in claim 1 , wherein the rasterizer is adapted for receiving a primitive defined by a plurality of vertices each including a W-value; and identifying an area based on the W-values, wherein the area is representative of a portion of a display to be drawn corresponding to the primitive.
Claim 20
Dependent Claim
132 words
A graphics pipeline system for graphics processing, comprising: (a) transform means adapted for being coupled to a buffer to receive vertex data therefrom, the transform means positioned on a single semiconductor platform for transforming the vertex data from object space to screen space; (b) lighting means positioned on the same single semiconductor platform as the transform means for performing lighting operations on the vertex data received from the transform means; and (c) rasterizer means positioned on the same single semiconductor platform as the transform means and lighting means for rendering the vertex data received from the lighting means; (d) wherein at least one of the transform means and the lighting means includes a sequencer means for executing multiple threads of operation in Parallel through each of a plurality of logic units thereof.
Claim 21
Dependent Claim
132 words
A graphics pipeline system for graphics processing, comprising: (a) transform means adapted for being coupled to a buffer to receive vertex data therefrom, the transform means positioned on a single semiconductor platform for transforming the vertex data from object space to screen space; (b) lighting means positioned on the same single semiconductor platform as the transform means for performing lighting operations on the vertex data received from the transform means; and (c) rasterizer means positioned on the same single semiconductor platform as the transform means and lighting means for rendering the vertex data received from the lighting means; (d) wherein at least one of the transform means and the lighting means includes a sequencer means for executing multiple threads of operation in Parallel through each of a plurality of logic units thereof.
Claim 22
Independent Claim
66 words
A method for graphics processing, comprising: (a) transforming vertex data from object space to screen space; (b) lighting the vertex data; (c) executing multiple threads of operation in parallel through a plurality of logic units while at least one of transforming and lighting the vertex data; and (d) rendering the vertex data, wherein the vertex data is transformed, lighted, and rendered on a single semiconductor platform.
Claim 23
Independent Claim
66 words
A method for graphics processing, comprising: (a) transforming vertex data from object space to screen space; (b) lighting the vertex data; (c) executing multiple threads of operation in parallel through a plurality of logic units while at least one of transforming and lighting the vertex data; and (d) rendering the vertex data, wherein the vertex data is transformed, lighted, and rendered on a single semiconductor platform.
Claim 24
Dependent Claim
59 words
The method as recited in claim 20 , wherein prior to rendering, the graphics processing avoids a clipping operation by: receiving a primitive defined by a plurality of vertices each including a W-value; and identifying an area based on the W-values, wherein the area is representative of a portion of a display to be drawn corresponding to the primitive.
Claim 25
Dependent Claim
98 words
A graphics pipeline system for graphics processing, comprising: (a) a lighting module adapted for being coupled to a transform module to receive vertex data therefrom, the lighting module being positioned on a single semiconductor platform for performing lighting operations on the vertex data received from the transform module; and (b) a rasterizer coupled to the lighting module and positioned on the same single semiconductor platform as the lighting module for rendering the vertex data received from the lighting module; (c) wherein a clipping operation is avoided prior to rasterization by the rasterizer using W-values of the vertex data.
Claim 26
Dependent Claim
98 words
A graphics pipeline system for graphics processing, comprising: (a) a lighting module adapted for being coupled to a transform module to receive vertex data therefrom, the lighting module being positioned on a single semiconductor platform for performing lighting operations on the vertex data received from the transform module; and (b) a rasterizer coupled to the lighting module and positioned on the same single semiconductor platform as the lighting module for rendering the vertex data received from the lighting module; (c) wherein a clipping operation is avoided prior to rasterization by the rasterizer using W-values of the vertex data.
Claim 27
Independent Claim
40 words
A method for graphics processing, comprising: (a) lighting vertex data; (b) avoiding a clipping operation using W-values of the vertex data; and (c) rendering the vertex data, wherein the vertex data is lighted and rendered on a single semiconductor platform.
Claim 28
Independent Claim
40 words
A method for graphics processing, comprising: (a) lighting vertex data; (b) avoiding a clipping operation using W-values of the vertex data; and (c) rendering the vertex data, wherein the vertex data is lighted and rendered on a single semiconductor platform.
Claim 29
Dependent Claim
84 words
A graphics pipeline system for graphics processing, comprising: (a) a transform module adapted for being coupled to a buffer to receive vertex data therefrom, the transform module being positioned on a single semiconductor platform for transforming the vertex data from object space to screen space; and (b) a rasterizer positioned on the same single semiconductor platform as the transform module for rendering the vertex data; (c) wherein a clipping operation is avoided prior to rasterization by the rasterizer using W-values of the vertex data.
Claim 30
Dependent Claim
84 words
A graphics pipeline system for graphics processing, comprising: (a) a transform module adapted for being coupled to a buffer to receive vertex data therefrom, the transform module being positioned on a single semiconductor platform for transforming the vertex data from object space to screen space; and (b) a rasterizer positioned on the same single semiconductor platform as the transform module for rendering the vertex data; (c) wherein a clipping operation is avoided prior to rasterization by the rasterizer using W-values of the vertex data.
Claim 31
Independent Claim
46 words
A method for graphics processing, comprising: (a) transforming vertex data from object space to screen space; (b) avoiding a clipping operation using W-values of the vertex data; and (c) rendering the vertex data, wherein the vertex data is transformed and rendered on a single semiconductor platform.
Claim 32
Independent Claim
46 words
A method for graphics processing, comprising: (a) transforming vertex data from object space to screen space; (b) avoiding a clipping operation using W-values of the vertex data; and (c) rendering the vertex data, wherein the vertex data is transformed and rendered on a single semiconductor platform.
Claim 33
Dependent Claim
59 words
The method as recited in claim 25 , wherein prior to rendering, the graphics processing avoids the clipping operation by: receiving a primitive defined by a plurality of vertices each including a W-value; and identifying an area based on the W-values, wherein the area is representative of a portion of a display to be drawn corresponding to the primitive.
References Cited (Backward Citations)
US5838337A
Cited
US6000027A
Cited
EP0690430A2
Cited
US5694143A
Cited
WO1998028695A1
Cited
US5977997A
Cited
WO1999052040A1
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-03-05 | 2004-09-04 | 2005-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-03-05 | 2008-09-04 | 2009-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-03-05 | 2012-09-04 | 2013-03-06 | $7700.00 | Window Closed / Lapsed |