EP0690430A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Single chip frame buffer and graphics accelerator
Assignee: Accelerix Ltd
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Filing: 1995-05-20
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Granted: —
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Expires: 2015-05-20
Abstract
Abstract A single chip display processor comprised of a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, a pixel data unit (PDU) for processing the pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, the IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process the blocks of pixel data for subsequent display of processed pixel data.
Inventors
- 👤 Dennis Fielder
- 👤 James Derbyshire
- 👤 Peter Gillingham
- 👤 Randy Torrance
- 👤 Cormac O'connell
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 16:45
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/363; G09G5/39; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4093; G11C11/4096; G11C7/00; G11C7/10; G11C7/1048; G11C2207/00; G11C2207/10; G11C2207/104
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
89 words
A single chip display processor comprising: (a) a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, (b) a pixel data unit (PDU) for processing said pixel data, integrated in the same integrated circuit (IC) chip as the DRAM, (c) said IC chip further comprising a massively parallel bus for transferring blocks of pixel data at the same time from the DRAM to the PDU, whereby the PDU can process said blocks of pixel data for subsequent display of processed pixel data.
Claim 2
Dependent Claim
135 words
A processor as defined in claim 1 in which said DRAM is comprised of rows of wordlines, columns of bitlines which are orthogonal to said rows of bitlines, bit storage cells connected to said bitlines and wordlines each for storage of a bit of said pixel data, and rows of sense amplifiers connected to the bitlines, sense amplifier select lines connected to groups of said sense amplifiers for enabling operation of said groups said sense amplifiers together, said sense amplifier and select lines being carried by said IC chip parallel to said wordlines, data bus lines constituting said massively parallel bus each being respectively connected to an output of a sense amplifier and being carried by said IC chip parallel to the bitlines, the PDUs being pitch matched to a predetermined number of bitline columns.
Claim 3
Dependent Claim
44 words
A processor as defined in claim 2 in which the PDU is comprised of plural PDU units, each unit being comprised of a single bit PDU processor, each PDU processor being connected to a databus for receiving a logical bit from a sense amplifier.
Claim 4
Dependent Claim
40 words
A processor as defined in claim 2 in which the PDU is pitch matched to four bitline columns, and being comprised of single bit PDU processors, each virtually simultaneously receiving a bit from a corresponding databus for parallel processing thereof.
Claim 5
Dependent Claim
63 words
A processor as defined in claim 3 including a PDU address decoder for enabling operation at the same time of any number of PDU processors having adjacent addresses, whereby any width of data from any adjacent bitlines may be written into said any number of PDU processors or any width of said number of PDU processors may be cleared in a single cycle.
Claim 6
Dependent Claim
87 words
A processor as defined in claim 3 in which each PDU unit is comprised of one-bit source, destination and brush variable registers, a four input raster operation (R0P4) circuit for logically operating on bits stored in said registers, an ROP4 register for storing output data of the ROP4 circuit, and a mask register for masking output data of the PDU processors, each register being connected to the ROP4 circuit, the ROP4 circuit and each register being pitch matched to four bitline columns and connected to a databus.
Claim 7
Dependent Claim
40 words
A processor as defined in claim 6 in which each of the source, destination and brush variable registers is comprised of a cross-coupled inverter connected to each data bus through a memory access circuit via a pair of NMOS transistors.
Claim 8
Dependent Claim
63 words
A processor as defined in claim 6 in which each of the source, destination and brush variable registers in two ported, and is comprised of a cross-coupled inverter connected from one port to a corresponding data bus through a memory circuit via a pair of NMOS transistors, and being connected from a second port to a register bus connected to the ROP4 circuit.
Claim 9
Dependent Claim
68 words
A processor as defined in claim 8 in which each inverter is comprised of VDD voltage power and VSS ground inputs, and further including, to implement a write cycle to an inverter, means for equalizing said power and ground inputs at a voltage of ½ VDD, applying input data to the register bus, selecting the register, then raising the power and ground inputs to VDD and VSS respectively.
Claim 10
Dependent Claim
24 words
A processor as defined in claim 9 including, to implement a read cycle, precharging the register bus to VDD prior to reading the register.
Claim 11
Dependent Claim
41 words
A processor as defined in claim 9 including, to implement a read cycle, applying in place of a power voltage of VDD, a VPP voltage which is greater than: an NMOS transistor operation threshold voltage (V t ) higher than VDD.
Claim 12
Dependent Claim
106 words
A processor as defined in claim 1, in which each of the PDUs is comprised of at least one register, each of the registers being comprised of a cross-coupled inverter connected via access means to a pair of databus lines, each inverter being comprised of VDD and VSS ground inputs, means for implementing a cycle accessing each inverter to the pair of data buslines by precharging the databus lines to a voltage intermediate the difference between VDD and VSS, selecting each register to connect its inverter to the pair of data bus lines, and then raising the power and ground inputs to VDD and VSS respectively.
Claim 13
Dependent Claim
15 words
A processor as defined in claim 12 in which said intermediate voltage is about VDD/2.
Claim 14
Dependent Claim
33 words
A processor as defined in claim 2, including means for temporarily storing data from the PDU in the sense amplifiers connected to the bitlines during intervals when the DRAM is not in use.
Claim 15
Dependent Claim
28 words
A processor as defined in claim 14 including means for transferring said data from the PDU to said sense amplifiers for temporary storage via the massively parallel bus.
Claim 16
Dependent Claim
179 words
A processor as defined in claim 2 in which each bitline column of the DRAM is comprised of plural transmitting and receiving sense amplifiers respectively, each connected to a bitline pair, said plural sense amplifiers being connected in parallel to an operational pair of data bus lines of an operational data bus, and further comprising a dummy data bus comprised of a dummy pair of data bus lines, means for enabling the plural transmitting sense amplifiers to dump data to the operational pair of data bus lines and for equalizing the voltage on a corresponding bitline pair to VDD/2 voltage, means for charging the dummy pair of databus lines in parallel with the operational pair of data bus lines, means for detecting when the charge on the dummy pair of databus lines is readable and for providing a signal for disabling the transmitting sense amplifiers and enabling the receiving sense amplifiers, whereby the voltage on the operational pair of data bus lines is inhibited from rising to a level higher than is necessary for correct reading of its data.
Claim 17
Dependent Claim
174 words
A DRAM comprised of bitlines, wordlines, data storage cells connected to the bitlines and wordlines, transmitting and receiving sense amplifiers connected to the bitlines, and data buses connected to said sense amplifiers, plural sense amplifiers being connected in parallel to an operational pair of data bus lines of an operational data bus, a dummy data bus comprised of a dummy pair of data bus lines, means for enabling plural transmitting sense amplifiers to dump data to the operational pair of data bus lines and for equalizing the voltage on a corresponding bitline pair to VDD/2, means for charging the dummy pair of databus lines in parallel with the operational pair of data bus lines, means for detecting when the charge on the dummy pair of databus lines is readable and for providing a signal for disabling the transmitting sense amplifiers and enabling the receiving sense amplifiers, whereby the voltage on the operational pair of data bus lines is inhibited from rising to a level higher than is necessary for correct reading of its data.
Claim 18
Dependent Claim
33 words
A processor as defined in claim 1, in which the DRAM memory is organized into separate buffer blocks, each block storing one bit of each pixel of an entire frame of multi-bit pixels.
Claim 19
Dependent Claim
55 words
A processor as defined in claim 18, including a system bus for carrying pixel bits from a system graphics processor for writing to each of the buffer blocks individually, and for carrying pixel bits from a system graphics processor for writing the same bits values in all of the buffer blocks in a broadcast mode.
Claim 20
Dependent Claim
24 words
A processor as defined in claim 18 including means for reading the buffer blocks in a fast page mode to provide output pixel data.
Claim 21
Dependent Claim
26 words
A processor as defined in claim 18 in which the buffer blocks are each at least 2560 columns wide by 544 rows deep in bit capacity.
Claim 22
Dependent Claim
37 words
A processor as defined in claim 18 in which the buffer blocks contain extra rows of memory for storage of at least one of scratchpad data, pixel color data, pattern data, text font data and video data.
Claim 23
Dependent Claim
26 words
A processor as defined in claim 18 in which the buffer blocks are each at least 2560 columns wide by 564 rows deep in bit capacity.
Claim 24
Dependent Claim
34 words
A processor as defined in claim 18, each buffer block comprising a DRAM and an associated PDU connected to the DRAM via said massively parallel bus, the PDU being pitch matched to the DRAM.
Claim 25
Dependent Claim
63 words
A processor as defined in claim 18, including a graphics out shift register, said shift register being pitch matched to the DRAM and being connected to the DRAM via the massively parallel bus, means for transferring data in parallel from the DRAM via said bus to the graphics out shift register and for outputting said transferred data serially for processing by display circuitry.
Claim 26
Dependent Claim
66 words
A processor as defined in claim 25 in which the shift register is comprised of a pair of shift register segments, means for transferring data corresponding to the sequential groups of pixels to each of the pairs of shift registers reciprocally in tandem whereby pixel data relating to a complete display line can be serially read out of the pairs of shift registers in sequential order.
Claim 27
Dependent Claim
44 words
A processor as defined in claim 26 including means for reading said data out of the shift register in parallel groups of bits, and means for operating the shift register in cycles at a rate which is a fraction of a pixel data rate.
Claim 28
Dependent Claim
72 words
A processor as defined in claim 26 further including a video out shift register connected to the massively parallel bus for receiving pixel data from the DRAM in parallel and for outputting the received pixel data serially for processing by display circuitry, and a video input shift register connected to the massively parallel bus for receiving serial video pixel data and for transferring it via the massively parallel bus to the DRAM.
Claim 29
Dependent Claim
77 words
A display processor comprising: (a) a dynamic random access memory (DRAM) for storing at least one of graphics and video pixel data, (b) a processor for processing at least one of said graphics and video input pixel data, (c) a random access memory digital to analog converter (RAMDAC) for receiving data processed by said processor and for converting it to a display signal, (d) said DRAM, processor and RAMDAC being integrated into the same integrated circuit chip.
Claim 30
Dependent Claim
30 words
A processor as defined in claim 29 including a pixel data unit (PDU) for processing blocks of said pixel data, said PDU being integrated into said same integrated circuit chip.
Claim 31
Dependent Claim
95 words
A display processor comprising: (a) a frame buffer for storing pixel data in rows, (b) an output logic circuit for processing said pixel data, (c) a massively parallel bus having as many bus lines as pixel bits in a row interconnecting the frame buffer and output logic circuit, (d) a random access memory digital to analog converter (RAMDAC) connected to the output logic circuit for connecting data processed by the output logic circuit to a display signal, (e) said frame buffer, output logic circuit, bus and RAMDAC being integrated into the same integrated circuit chip.
Claim 32
Independent Claim
73 words
A method of providing pixel data in a display processor system comprising: (a) storing pixel data in a frame buffer, (b) transferring pixel data from a row of the frame buffers in parallel via a massively parallel bus having similar number of bus lines as pixel bits to be transferred to corresponding parallel inputs of a graphics output shift register, and (c) serially reading the data from the shift register to display circuitry.
Claim 33
Dependent Claim
150 words
A method as defined in claim 32 in which the shift register is comprised of a pair of register segments each pitch matched to the frame buffer wherein each bit storage location of the shift register is matched to a predetermined number of columns of the frame buffer, and further including the step of (i) transferring sequential pixel display data in parallel from the frame buffer to one of the pair of register segments, (ii) initiating serial readout of the one register segment, (iii) transferring subsequent sequential pixel display data to the other of the pair of register segments, (iv) initiating serial readout of said other of the pair of register segments after the first of the pair of register segments has been read, and repeating steps (i), (ii), (iii) and (iv) repeatedly until all pixel data for a frame of the display has been transferred to the shift register.
Claim 34
Dependent Claim
56 words
A method as defined in claim 33 in which the frame buffer is 2560 bit storage columns wide, in which each register segment is 320 bits wide and in which the transferring steps are carried out via a massively parallel bus carrying said data from the columns to the register segments which has 1280 bus lines.
Claim 35
Dependent Claim
28 words
A method as defined in claim 33, including the step of reading the data from the shift register to display circuitry several bits in parallel at a time.
Claim 36
Dependent Claim
47 words
A method as defined in claim 32 including the steps of transferring data from a row of the frame buffer into a pixel data unit (PDU) via the massively parallel bus, processing the pixel data in the PDU and storing the processed data in the frame buffer.
Claim 37
Dependent Claim
47 words
A method as defined in claim 36, in which at least one of storing the pixel data in the frame buffer, transferring the data into the PDU and transferring the data from the frame buffer into said shift register is controlled by addressing via a range decoder.
Claim 38
Dependent Claim
62 words
A method as defined in claim 36 in which the frame buffer is comprised of a dynamic random access memory (DRAM) having plural bitline sense amplifiers connected to the massively parallel bus, and including the step of temporarily storing data from the PDU in the bitline sense amplifiers whereby the bitline sense amplifiers are used as temporary storage registers for the PDU.
References Cited (Backward Citations)
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