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Patent US6198329B1 successfully refreshed from Google Patents.
US6198329B1
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Auto zero circuitry and associated method
Assignee: Maxim Integrated Products Inc
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Filing: 1999-11-12
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Granted: 2001-03-06
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Expires: 2019-11-12
Abstract
Abstract A circuit and associated method for determining the offset bias of a comparator by first shorting together the inputs of the comparator to apply the same voltage signal at each of the inputs of the comparator. The voltage signal at one of the inputs is then offset a select amount by applying varying selected resistances from a variable resistor to the comparator. The variable resistor is controlled by a programmable controller that is responsive to an input clock signal. At each selected amount of offset applied to the input, the output is monitored to determine if the output of the comparator has flipped, or changed state. When the output flips, the corresponding resistance setting is used to compensate for the corresponding offset bias of the comparator.
Inventors
- 👤 William Richard Ezell
- 👤 Robert Mounger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 18:01
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/45; H03F3/45071; H03F3/45076; H03F3/45179; H03F3/45183; H03F3/45479; H03F3/45632; H03F3/45744; H03F3/45766; H03F3/45771; H03K; H03K5/00; H03K5/22; H03K5/24; H03K5/2472; H03K5/2481; H03F2203/00; H03F2203/45; H03F2203/45674; H03F2203/45726
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
120 words
A circuit for determining offset bias of a comparator having at least two inputs and an output with each of the at least two inputs shortable together to receive the same initial signal, said circuit comprising: a variable resistor bank connectable to the comparator, said variable resistor bank comprising a plurality of resistive branches; and a controller connected to said resistor bank, said controller responsive to an input signal to thereby select at least one of said plurality of resistive branches and to thereby vary the resistance of said resistor bank such that an offset bias of the comparator of the first input being determined when the output of the comparator flips for a corresponding resistance of said resistor bank.
Claim 2
Dependent Claim
120 words
A circuit for determining offset bias of a comparator having at least two inputs and an output with each of the at least two inputs shortable together to receive the same initial signal, said circuit comprising: a variable resistor bank connectable to the comparator, said variable resistor bank comprising a plurality of resistive branches; and a controller connected to said resistor bank, said controller responsive to an input signal to thereby select at least one of said plurality of resistive branches and to thereby vary the resistance of said resistor bank such that an offset bias of the comparator of the first input being determined when the output of the comparator flips for a corresponding resistance of said resistor bank.
Claim 3
Dependent Claim
13 words
The circuit as recited in claim 1 , wherein said controller is programmable.
Claim 4
Dependent Claim
202 words
A circuit for determining offset bias of a comparator having a first and second input and an output, with each of the inputs being configurable to receive the same voltage signal, said circuit comprising: a first variable resistor bank coupled to the comparator, said first variable resistor bank including an output for outputting varying resistances for biasing the voltage signal received at the first input of the comparator; a second variable resistor bank coupled to the comparator, said second variable resistor bank including an output for outputting varying resistances for biasing the voltage signal received at the second input of the comparator; and a controller coupled to said first and second variable resistor banks, said controller responsive to an input signal for controlling the varying resistances outputted by at least one of said first and second variable resistor banks, such that the offset bias of the comparator of the first input being determined when the output of the comparator flips for a corresponding selected resistance of said first variable resistor bank and the offset bias of the comparator for the second input being determined when the output of the comparator flips for a corresponding selected resistance of said second variable resistor bank.
Claim 5
Dependent Claim
202 words
A circuit for determining offset bias of a comparator having a first and second input and an output, with each of the inputs being configurable to receive the same voltage signal, said circuit comprising: a first variable resistor bank coupled to the comparator, said first variable resistor bank including an output for outputting varying resistances for biasing the voltage signal received at the first input of the comparator; a second variable resistor bank coupled to the comparator, said second variable resistor bank including an output for outputting varying resistances for biasing the voltage signal received at the second input of the comparator; and a controller coupled to said first and second variable resistor banks, said controller responsive to an input signal for controlling the varying resistances outputted by at least one of said first and second variable resistor banks, such that the offset bias of the comparator of the first input being determined when the output of the comparator flips for a corresponding selected resistance of said first variable resistor bank and the offset bias of the comparator for the second input being determined when the output of the comparator flips for a corresponding selected resistance of said second variable resistor bank.
Claim 6
Dependent Claim
13 words
The circuit as recited in claim 3 , wherein said controller is programmable.
Claim 7
Dependent Claim
47 words
The circuit as recited in claim 4 , wherein: said first variable resistor bank comprisies a plurality of resistive branches; and said controller includes a plurality of transistors, each of said plurality of transistors being coupled to separate resistive branches included in said plurlaity of resistive branches.
Claim 8
Dependent Claim
50 words
The circuit as recited in claim 5 , wherein: said controller includes a plurality of logic gates, with each of said plurality of logic gates being coupled to a separate one of said plurality of transistors, each of said plurality of logic gates for controllably selecting said plurality of transistors.
Claim 9
Dependent Claim
18 words
The circuit of claim 1 , wherein each of said plurality of resistive branches have different resistive values.
Claim 10
Dependent Claim
19 words
The circuit of claim 7 , wherein each of said plurality of resistive branches comprise at least one resistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-03-05 | 2004-09-04 | 2005-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-03-05 | 2008-09-04 | 2009-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-03-05 | 2012-09-04 | 2013-03-06 | $7700.00 | Window Closed / Lapsed |