Auto zero circuitry and associated method

Claim 2

A circuit for determining offset bias of a comparator having at least two inputs and an output with each of the at least two inputs shorted together to receive the same initial signal, said circuit comprising: a variable resistor connected to the comparator, said variable resistor including an output for outputting varying resistances for biasing the initial signal received at a first of the at least two inputs of the comparator; a programmable controller connected to said variable resistor, said controller responsive to an input signal for controlling the varying resistances outputted by said variable resistor such that an offset bias of the comparator of the first input being determined when the output of the comparator flips for a corresponding selected resistance of said variable resistor; said variable resistor including at least two input taps, each of said at least two input taps selectable by said controller, such that if a first of said at least two input taps is selected by said controller a first resistance is outputted, and if a second of said at least two input taps is selected by said controller a second resistance is outputted, and if each of said at least two input taps is selected by said controller, a third resistance is outputted; said controller including at least two transistors, with each of said at least two transistors being coupled to a separate one of said at least two input taps of said variable resistor, each of said at least two transistors for selecting at least two input taps of said variable resistor; and said controller further including at least two logic nand gates, each of said at least two logic nand gates being coupled to a separate one of said at least two transistors, each of said at least two logic nand gates being responsive to the input signal and for controlling said at least two transistors selecting said at least two input taps of said variable resistor.

Claim 3

The circuit as recited in claim 1, and further comprising: a second variable resistor connected to the comparator, said second variable resistor including an output for outputting varying resistances for biasing the initial signal received at a second of the at least two inputs of the comparator; and a second controller connected to said second variable resistor, said controller responsive to the input signal for controlling the varying resistances outputted by said second variable resistor such that an offset bias of the second input of the comparator being determined when the output of the comparator flips for a corresponding selected resistance of said second variable resistor.

Claim 4

The circuit as recited in claim 2, wherein: said second variable resistor includes at least two input taps, each of said at least two input taps of said second variable resistor selectable by said second controller, wherein if a first of said at least two input taps of said second variable resistor is selected by said second controller a fourth resistance is outputted, and further wherein if a second of said at least two input taps of said second variable resistor is selected by said second controller a fifth resistance is outputted, and further wherein if each of said at least two input taps of said second variable resistor are selected by said second controller a sixth resistance is outputted.

Claim 5

The circuit as recited in claim 2, wherein said second controller is programmable.

Claim 6

The circuit as recited in claim 3, wherein said second controller includes at least two transistors, with each of said at least two transistors of said second controller being coupled to a separate one of said at least two input taps of said second variable resistor, each of said at least two transistors of said second controller for selecting said at least two input taps of said second variable resistor.

Claim 7

The circuit as recited in claim 5, wherein said second controller at least two logic nand gates, with each of said at least two logic nand gates of said second controller coupled to a separate one of said at least two transistors of said second controller, each of said at least two logic nand gates of said second controller being responsive to the input signal and for controlling said at least two transistors of said second controller selecting said at least two input taps of said second variable resistor.

Claim 8

A circuit for determining offset bias of a comparator having first and second inputs and first and second outputs, with each of the inputs shorted together to receive the same voltage signal, said circuit comprising: a first variable resistor coupled to the comparator, said first variable resistor including an output for outputting varying resistances for biasing the voltage signal received at the first input of the comparator; a second variable resistor coupled to the comparator, said second variable resistor including an output for outputting varying resistances for biasing the voltage signal received at the second input of the comparator; a programmable controller coupled to said first and second variable resistors, said controller responsive to an input signal for controlling the varying resistances outputted by said first and second variable resistors, such that the offset bias of the comparator of the first input being determined when the output of the comparator flips for a corresponding selected resistance of said first variable resistor and the offset bias of the comparator for the second input being determined when the output of the comparator flips for a corresponding selected resistance of said second variable resistor; each of said first and second variable resistors including at least two input taps, each of said at least two input taps for said first and second variable resistors being individually selectable by said controller to produce varying resistances outputted by said first and second variable resistors; said controller including a plurality of transistors, each of said plurality of transistors being coupled to a separate input tap of said each of said at least two input taps of said first and second variable resistors, said transistors for selecting said input taps of said first and second variable resistors; and said controller further including a plurality of logic nand gates, with each of said plurality of logic nand gates being coupled to a separate one of said plurality of transistors, each of said plurality of logic nand gates for controllably selecting said plurality of transistors.

Claim 9

A circuit for determining offset bias of a comparator having first and second inputs and first and second outputs, with each of the inputs shorted together to receive the same voltage signal, said circuit comprising: a first variable resistor coupled to the comparator, said first variable resistor including an output for outputting varying resistances for biasing the voltage signal received at the first input of the comparator; a second variable resistor coupled to the comparator, said second variable resistor including an output for outputting varying resistances for biasing the voltage signal received at the second input of the comparator; a programmable controller coupled to said first and second variable resistors, said controller responsive to an input signal for controlling the varying resistances outputted by said first and second variable resistors, such that the offset bias of the comparator of the first input being determined when the output of the comparator flips for a corresponding selected resistance of said first variable resistor and the offset bias of the comparator for the second input being determined when the output of the comparator flips for a corresponding selected resistance of said second variable resistor; each of said first and second variable resistors including at least two input taps, each of said at least two input taps for said first and second variable resistors being individually selectable by said controller to produce varying resistances outputted by said first and second variable resistors; said controller including a plurality of transistors, each of said plurality of transistors being coupled to a separate input tap of said each of said at least two input taps of said first and second variable resistors, said transistors for selecting said input taps of said first and second variable resistors; and said controller further including a plurality of logic nand gates, with each of said plurality of logic nand gates being coupled to a separate one of said plurality of transistors, each of said plurality of logic nand gates for controllably selecting said plurality of transistors.