US4591740A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multiple input port circuit having temperature zero voltage offset bias means
Assignee: Burr Brown Research Corp
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Filing: 1983-02-28
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Granted: 1986-05-27
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Expires: 2003-02-28
Abstract
Abstract A plurality of input stages having their outputs connected to provide differential currents to a load. When a bias current flows through a selected one of the input stages, the differential currents are provided in response to a differential signal provided to the selected stage. The input stages are each comprised of a pair of emitter-coupled transistors. Resistors are connected in series with the emitters of the transistors and the bias current is directly proportional to absolute temperature. The resistors may be adjusted to cause the offset voltages of the input stages to substantially equal zero at all temperatures.
Inventors
- 👤 Thomas R. Anderson
- 👤 Howard L. Skolnik
- 👤 Bruce C. Trump
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:31
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/62; H03K17/6257; H03K17/6264
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
208 words
Apparatus for selectively providing differential output signals to a load circuit comprising: a plurality of differential input stages receiving input signals, all of said input stages coupled to said load circuit, each of said input stages applying differential output signals to said load circuit when a bias current flows through said amplifier stage and said load circuit; switching means associated with each of said input stages for providing a bias current to said associated input stage when a switching signal is applied thereto, said bias current also flowing through said load circuit; wherein said input stages comprise: first and second transistors connected to said load circuit wherein an input signal is a difference between two signals respectively provided to the bases to said transistors; a first resistor coupled in series with the emitter of said first transistor; a second resistor coupled in series with the emitter of said second transistor and to said first resistor, said resistors having values that cause the offset voltage of said input stage to be substantially equal to zero; and transistor means in emitter current paths of said first and said second transistors for providing a flow of emitter currents through said transistors and compensating for the temperature dependence of said emitter currents.
Claim 2
Dependent Claim
208 words
Apparatus for selectively providing differential output signals to a load circuit comprising: a plurality of differential input stages receiving input signals, all of said input stages coupled to said load circuit, each of said input stages applying differential output signals to said load circuit when a bias current flows through said amplifier stage and said load circuit; switching means associated with each of said input stages for providing a bias current to said associated input stage when a switching signal is applied thereto, said bias current also flowing through said load circuit; wherein said input stages comprise: first and second transistors connected to said load circuit wherein an input signal is a difference between two signals respectively provided to the bases to said transistors; a first resistor coupled in series with the emitter of said first transistor; a second resistor coupled in series with the emitter of said second transistor and to said first resistor, said resistors having values that cause the offset voltage of said input stage to be substantially equal to zero; and transistor means in emitter current paths of said first and said second transistors for providing a flow of emitter currents through said transistors and compensating for the temperature dependence of said emitter currents.
Claim 3
Dependent Claim
100 words
Apparatus according to claim 1 wherein said emitter currents of said transistors are substantially equal and in accordance with a temperature dependence relationship at all temperatures of interest, said relationship being given as: (Kt/g)·ln D=Ie1 ·ΔR where: K is Boltzman's constant; T is absolute temperature; Ie1 is the emitter current of the first transistor; q is the charge of an electron; and D=(Ie1/Is1)/(Ie2/Is2) where: Is1 is the saturation current of the base-emitter junction of the first transistor; Is2 is the saturation current of the base-emitter junction of the second transistor; and Ie2 is the emitter current of the second transistor.
Claim 4
Dependent Claim
53 words
Apparatus according to claim 1 including a pair of transistors, the emitters of said first and second transistors being coupled together via said pair of resistors and the base terminals of said pair of transistors, said pair of transistors coupled to said load circuit for applying said bias current to said load circuit.
Claim 5
Dependent Claim
71 words
Apparatus according to claim 3 wherein said switching means comprises: a diverting current source coupled to said associated input stage, said diverting current source providing a current at least as great as said bias current; a switch coupled in series with said diverting current source, said bias current being diverted from said associated input stage and said load circuit to said diverting current source in response to closure of said switch.
Claim 6
Dependent Claim
96 words
Apparatus according to claim 4 wherein said load circuit comprises a current mirror, each of said input stage including a pair of emitter-coupled transistors coupled as a differential amplifier emitter terminals of each of said transistors coupled through a variable resistor and a biasing transistor to a different terminal of said current mirror, each of said input stages further including a first current source for biasing said biasing transistor, and wherein said switching means includes a fifth transistor coupled to said transistor pair and a switch coupled to said fifth transistor and a second current source.
Claim 7
Independent Claim
134 words
The method of providing differential output signals in response to a selected one of a plurality of differential input signals comprising the steps of: providing a plurality of input stages, each of said input stages having a pair of transistors with their emitters coupled, said input stages providing differential output signals to a load circuit by means of a bias current flowing through said input stages and said load circuits; applying said input signals respectively to said input stages; and supplying said bias current to a selected one of said input stages to cause said differential output signals to be provided to said load circuit in response to differential input signals applied to said selected input stage, and causing the offset voltage of said selected input stage to equal zero at substantially all temperatures.
Claim 8
Independent Claim
134 words
The method of providing differential output signals in response to a selected one of a plurality of differential input signals comprising the steps of: providing a plurality of input stages, each of said input stages having a pair of transistors with their emitters coupled, said input stages providing differential output signals to a load circuit by means of a bias current flowing through said input stages and said load circuits; applying said input signals respectively to said input stages; and supplying said bias current to a selected one of said input stages to cause said differential output signals to be provided to said load circuit in response to differential input signals applied to said selected input stage, and causing the offset voltage of said selected input stage to equal zero at substantially all temperatures.
Claim 9
Independent Claim
197 words
The method of providing differential output signals in response to a selected one of a plurality of differential input signals comprising the steps of: providing a plurality of input stages, each of said input stages having a pair of transistors with their emitters coupled, said input stages providing differential output signals to a load circuit by means of a bias current flowing through said input stage and said load circuit; applying said input signals respectively to said input stages; supplying said bias current to a selected one of said input stages to cause said differential output signals to be provided to said load circuit in response to differential input signals applied to said selected input stage; and diverting said bias current from said selected stage when said stage is no longer selected wherein said step of supplying includes the step of supplying a bias current directly proportional to temperature and the additional steps of: providing a pair of resistors, each of said transistors is coupled in series with one of said emitters; and adjusting said resistors to cause the offset voltage of said stage to be substantially equal to zero when said bias current is supplied thereto.
Claim 10
Independent Claim
197 words
The method of providing differential output signals in response to a selected one of a plurality of differential input signals comprising the steps of: providing a plurality of input stages, each of said input stages having a pair of transistors with their emitters coupled, said input stages providing differential output signals to a load circuit by means of a bias current flowing through said input stage and said load circuit; applying said input signals respectively to said input stages; supplying said bias current to a selected one of said input stages to cause said differential output signals to be provided to said load circuit in response to differential input signals applied to said selected input stage; and diverting said bias current from said selected stage when said stage is no longer selected wherein said step of supplying includes the step of supplying a bias current directly proportional to temperature and the additional steps of: providing a pair of resistors, each of said transistors is coupled in series with one of said emitters; and adjusting said resistors to cause the offset voltage of said stage to be substantially equal to zero when said bias current is supplied thereto.
Claim 11
Dependent Claim
131 words
A circuit for providing a differential output signal to a load circuit in response to a differential input signal comprising: a first transistor connected to said load; a second transistor connected to said load, the emitters of said transistors being coupled, said input signal being applied to the bases of said transistors, a current source coupled to said first and said second transistor, said current source providing a flow of bias current through said transistors in direct proportion to absolute temperature; and a first resistor connected in series with the emitter of said first transistor; and a second resistor connected in series with the emitter of said second transistor, said resistors having values that cause said output signals to be zero when said input signal is zero at substantially all temperatures.
Claim 12
Dependent Claim
131 words
A circuit for providing a differential output signal to a load circuit in response to a differential input signal comprising: a first transistor connected to said load; a second transistor connected to said load, the emitters of said transistors being coupled, said input signal being applied to the bases of said transistors, a current source coupled to said first and said second transistor, said current source providing a flow of bias current through said transistors in direct proportion to absolute temperature; and a first resistor connected in series with the emitter of said first transistor; and a second resistor connected in series with the emitter of said second transistor, said resistors having values that cause said output signals to be zero when said input signal is zero at substantially all temperatures.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-26 | 1989-11-25 | 1990-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-26 | 1993-11-25 | 1994-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-26 | 1997-11-25 | 1998-05-27 | $7700.00 | Window Closed / Lapsed |