US6190944B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stacked package for semiconductor device and fabrication method thereof, and apparatus for making the stacked package
Assignee: SK Hynix Inc
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Filing: 1999-05-19
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Granted: 2001-02-20
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Expires: 2019-05-19
Abstract
Abstract A stacked semiconductor package with ultrahigh integration and a fabrication method thereof according to the present invention are provided to meet the requirements of a system device of being miniaturized and light-weighted and having high efficiency. Also, there is provide a jig for package aligning to fabricate the stacked semiconductor package. The semiconductor package according to the present invention is fabricated by mounting a second-type package including a molding portion and leads exposed at a lower surface of the molding portion of the second-type package on a first-type package including a molding portion and leads, each of being formed in a ‘J’ shape, which are respectively extended out of both sides of the molding portion. Here, uppermost surfaces of the leads of the first-type package are welded by solder to bottom surfaces of the leads of the second-type package. The stacked semiconductor package according to the present invention has advantages in which work process is relatively short compared to the conventional art and also package fabrication costs are reduced.
Inventors
- 👤 Chang Kuk Choi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 18:43
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/40; H10W70/411; H10W70/415; H10W90/00; H10W72/00; H10W72/071; H10W72/075; H10W72/851; H10W72/853; H10W72/865; H10W72/90; H10W72/951; H10W74/00; H10W90/701; H10W90/721; H10W90/722; H10W90/731; H10W90/736; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
242 words
A method for fabricating a stacked semiconductor package, comprising the steps of: fabricating a first-type package including a semiconductor chip having a plurality of pads on a center portion of an upper surface thereof, leads of which end portions are attached on the upper surface of the semiconductor chip at outer sides of the pads and the other end portions are externally extended from the semiconductor chip, wires for connecting the ends portions of the leads to the corresponding pads, and a molding portion covering the semiconductor chip, the wires and portions of the leads; fabricating a second-type package including a semiconductor chip having a plurality of pads on a center portion of a lower surface thereof, leads each of which consists of a chip-attached portion, a substrate-attached portion and a connecting portion and is formed in a ‘S’ shape, top surfaces of the chip-attached portions of the leads being respectively attached to portions of the lower surface of the semiconductor chip at the outer sides of the pads, wires for connecting end portions of the chip-attached portions to the corresponding pads, and a molding portion covering the semiconductor chip, the pads, the wires, and the chip-attached portions and the connecting portions of the leads; and welding the lower surfaces of the substrate-attached portions of the leads of the second-type package to upper surfaces of the portions of the leads of the first-type package which are not covered by the molding portion.
Claim 2
Independent Claim
242 words
A method for fabricating a stacked semiconductor package, comprising the steps of: fabricating a first-type package including a semiconductor chip having a plurality of pads on a center portion of an upper surface thereof, leads of which end portions are attached on the upper surface of the semiconductor chip at outer sides of the pads and the other end portions are externally extended from the semiconductor chip, wires for connecting the ends portions of the leads to the corresponding pads, and a molding portion covering the semiconductor chip, the wires and portions of the leads; fabricating a second-type package including a semiconductor chip having a plurality of pads on a center portion of a lower surface thereof, leads each of which consists of a chip-attached portion, a substrate-attached portion and a connecting portion and is formed in a ‘S’ shape, top surfaces of the chip-attached portions of the leads being respectively attached to portions of the lower surface of the semiconductor chip at the outer sides of the pads, wires for connecting end portions of the chip-attached portions to the corresponding pads, and a molding portion covering the semiconductor chip, the pads, the wires, and the chip-attached portions and the connecting portions of the leads; and welding the lower surfaces of the substrate-attached portions of the leads of the second-type package to upper surfaces of the portions of the leads of the first-type package which are not covered by the molding portion.
Claim 3
Dependent Claim
104 words
The method for fabricating the stacked semiconductor package according to claim 1 , wherein the step of welding the lower surfaces of the substrate-attached portions of the leads of the second-type package to the upper surfaces of the portions of the leads of the first-type package which are not covered by the molding portion comprises: applying a flux to the lower surfaces of the substrate-attached portions of the leads of the second-type package; attaching a plurality of solder balls to the flux; mounting the second-type package on the first-type package so as to align the corresponding leads thereof; and reflowing for the solder balls.
Claim 4
Dependent Claim
26 words
The method for fabricating the stacked semiconductor package according to claim 1 , wherein a material of the first and second-type packages is a solder resist.
Claim 5
Dependent Claim
40 words
The method for fabricating the stacked semiconductor package according to claim 1 , further comprising: applying an adhesive member to an upper surface of the molding portion of the second-type package before mounting the second-type package on the first-type package.
Claim 6
Dependent Claim
88 words
The method for fabricating the stacked semiconductor package according to claim 1 , wherein the step of fabricating the first-type package comprises: preparing a semiconductor chip which has a plurality of pads on a center portion of an upper surface thereof; attaching a plurality of leads at outer sides of the pads on the upper surface of the semiconductor chip; connecting the pads to the leads, respectively, by wires; and forming a molding portions for covering the semiconductor chip, the pads, the wires and portions of the leads.
Claim 7
Independent Claim
355 words
A method for fabricating a stacked semiconductor package, comprising the steps of: preparing a jig for package aligning including a substrate consisting of an insulating body having a predetermined height, a plurality of cavities formed at an upper portion of the body, through holes respectively formed in the cavities and penetrating the body, and align poles disposed at marginal portions of both sides of the body, and an align mask having a mask body, a plurality of openings penetrating the mask body and align holes formed in each corner of marginal portions of the mask body, wherein the align mask is attached on an upper surface of the substrate; placing a first-type package in each cavity, the first-type package including a semiconductor chip having a plurality of pads on a center portion of an upper surface thereof, leads of which end portions are attached on the upper surface of the semiconductor chip at outer sides of the pads and the other end portions are externally extended from the semiconductor chip, wires for connecting the ends portions of the leads to the corresponding pads, and a molding portion covering the semiconductor chip, the wires and portions of the leads; preparing a second-type package consisting of a semiconductor chip having a plurality of pads on a center portion of a lower surface thereof, leads each of which consists of a chip-attached portion, a substrate-attached portion and a connecting portion and is formed in a ‘S’ shape, top surfaces of the chip-attached portions of the leads being respectively attached to portions of the lower surface of the semiconductor chip at the outer sides of the pads, wires for connecting end portions of the chip-attached portions to the corresponding pads, and a molding portion covering the semiconductor chip, the pads, the wires, and the chip-attached portions and the connecting portions of the leads; attaching a plurality of solder balls to the lower surfaces of the substrate-attached portions of the leads of the second-type package; mounting the second-type package on the first-type package disposed in each opening of the jig for the package aligning; and reflowing for the solder balls.
Claim 8
Independent Claim
355 words
A method for fabricating a stacked semiconductor package, comprising the steps of: preparing a jig for package aligning including a substrate consisting of an insulating body having a predetermined height, a plurality of cavities formed at an upper portion of the body, through holes respectively formed in the cavities and penetrating the body, and align poles disposed at marginal portions of both sides of the body, and an align mask having a mask body, a plurality of openings penetrating the mask body and align holes formed in each corner of marginal portions of the mask body, wherein the align mask is attached on an upper surface of the substrate; placing a first-type package in each cavity, the first-type package including a semiconductor chip having a plurality of pads on a center portion of an upper surface thereof, leads of which end portions are attached on the upper surface of the semiconductor chip at outer sides of the pads and the other end portions are externally extended from the semiconductor chip, wires for connecting the ends portions of the leads to the corresponding pads, and a molding portion covering the semiconductor chip, the wires and portions of the leads; preparing a second-type package consisting of a semiconductor chip having a plurality of pads on a center portion of a lower surface thereof, leads each of which consists of a chip-attached portion, a substrate-attached portion and a connecting portion and is formed in a ‘S’ shape, top surfaces of the chip-attached portions of the leads being respectively attached to portions of the lower surface of the semiconductor chip at the outer sides of the pads, wires for connecting end portions of the chip-attached portions to the corresponding pads, and a molding portion covering the semiconductor chip, the pads, the wires, and the chip-attached portions and the connecting portions of the leads; attaching a plurality of solder balls to the lower surfaces of the substrate-attached portions of the leads of the second-type package; mounting the second-type package on the first-type package disposed in each opening of the jig for the package aligning; and reflowing for the solder balls.
Claim 9
Dependent Claim
43 words
The method for fabricating the stacked semiconductor package according to claim 6 , further comprising: applying a flux to the lower surfaces of the substrate-attached portions of the leads of the second-type package before attaching the solder balls to the lower surfaces thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-02-20 | 2004-08-21 | 2005-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-02-20 | 2008-08-21 | 2009-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-02-20 | 2012-08-21 | 2013-02-20 | $7700.00 | Window Closed / Lapsed |