US6184097B1 — Process for forming ultra-shallow source/drain ex…

Claim 1

Independent Claim 162 words

A method of manufacturing an integrated circuit, comprising: providing a gate structure on a semiconductor substrate, the gate structure including a pair of sacrificial spacers, only one of the sacrificial spacers being on each side of the gate structure; providing a deep source region and a deep drain region, the gate structure being between the deep source region and the deep drain region, the deep source region and the deep drain region not including extensions; siliciding the deep source region, the deep drain region, and the gate structure; removing the sacrificial spacers from above a portion of the semiconductor substrate to leave a plurality of holes; forming an amorphous region through the holes within the portion of the semiconductor substrate and exclusive of the deep drain region and the deep source region, wherein the amorphous region is formed by ion implantation; and providing dopants to the amorphous region, thereby forming the extensions to the deep source region and the deep drain region.

Claim 2

Independent Claim 162 words

A method of manufacturing an integrated circuit, comprising: providing a gate structure on a semiconductor substrate, the gate structure including a pair of sacrificial spacers, only one of the sacrificial spacers being on each side of the gate structure; providing a deep source region and a deep drain region, the gate structure being between the deep source region and the deep drain region, the deep source region and the deep drain region not including extensions; siliciding the deep source region, the deep drain region, and the gate structure; removing the sacrificial spacers from above a portion of the semiconductor substrate to leave a plurality of holes; forming an amorphous region through the holes within the portion of the semiconductor substrate and exclusive of the deep drain region and the deep source region, wherein the amorphous region is formed by ion implantation; and providing dopants to the amorphous region, thereby forming the extensions to the deep source region and the deep drain region.

Claim 3

Dependent Claim 23 words

The method of claim 1 further comprising: activating the dopants in annealing process at a temperature less than or equal to 600° C.

Claim 4

Dependent Claim 16 words

The method of claim 2 , wherein the annealing process operates at less than 600° C.

Claim 5

Dependent Claim 14 words

The method of claim 3 , wherein the removing step is a dry-etching step.

Claim 6

Dependent Claim 12 words

The method of claim 4 , wherein the sacrificial spacers comprise nitride.

Claim 7

Dependent Claim 12 words

The method of claim 1 wherein the siliciding step includes providing titanium.

Claim 8

Dependent Claim 14 words

The method of claim 1 , wherein the gate structure includes a polysilicon conductor.

Claim 9

Dependent Claim 20 words

The method of claim 1 further comprising: covering at least a portion of the semiconductor substrate with an insulative layer.

Claim 10

Dependent Claim 24 words

The method of claim 1 , wherein the extensions have depths of less than 30 nm from a top surface of the semiconductor substrate.

Claim 11

Dependent Claim 15 words

The method of claim 9 , wherein the amorphous region is approximately 20-40 nm deep.

Claim 12

Independent Claim 169 words

A method of manufacturing an ultra-large scale integrated circuit including a plurality of field effect transistors having shallow source and drain extensions, the method comprising the steps of: providing at least part of a gate structure including a pair of dummy spacers on a top surface of a semiconductor substrate, the gate structure disposed between a deep source and a deep drain, the deep source and deep drain not including the shallow source and drain extensions, the gate structure including a single dummy spacer of the dummy spacers on each side of the gate structure; siliciding the deep source and the deep drain; removing the dummy spacers to form a first hole and a second hole; providing a silicon or germanium semiconductor implant through the first hole and through the second hole to amorphize the semiconductor substrate exclusive of the deep source and the deep drain; and then providing a dopant implant through the first hole and through the second hole to form the shallow source and drain extensions.

Claim 13

Independent Claim 169 words

A method of manufacturing an ultra-large scale integrated circuit including a plurality of field effect transistors having shallow source and drain extensions, the method comprising the steps of: providing at least part of a gate structure including a pair of dummy spacers on a top surface of a semiconductor substrate, the gate structure disposed between a deep source and a deep drain, the deep source and deep drain not including the shallow source and drain extensions, the gate structure including a single dummy spacer of the dummy spacers on each side of the gate structure; siliciding the deep source and the deep drain; removing the dummy spacers to form a first hole and a second hole; providing a silicon or germanium semiconductor implant through the first hole and through the second hole to amorphize the semiconductor substrate exclusive of the deep source and the deep drain; and then providing a dopant implant through the first hole and through the second hole to form the shallow source and drain extensions.

Claim 14

Dependent Claim 13 words

The method of claim 11 , wherein the siliciding step includes nickel deposition.

Claim 15

Dependent Claim 15 words

The method of claim 12 further comprising: providing a silicon dioxide layer over the silicide.

Claim 16

Dependent Claim 22 words

The method of claim 11 , wherein the step of providing a silicon or germanium semiconductor implant creates an amorphous silicon region.

Claim 17

Dependent Claim 23 words

The method of claim 11 , further comprising: activating dopants associated with the dopant implant at a temperature of 600° C. or less.

Claim 18

Dependent Claim 25 words

The method of claim 15 , wherein the dummy spacers are a silicon nitride material, the silicon nitride material being stripped in a dry-etching process.

Claim 19

Dependent Claim 142 words

A process for forming shallow source extensions and shallow drain extensions on a substrate, the process comprising: forming a plurality of gate structures on a top surface of the substrate, each gate structure including a single pair of spacers; forming deep source drain regions on each side of the gate structures, the deep source drain regions not including the shallow source extensions and the shallow drain extensions; siliciding the deep source drain regions; removing the single pair of spacers from each gate structure, thereby exposing the top surface of the substrate; and implanting silicon or germanium through the exposed top surface of the substrate to form amorphous silicon regions exclusive of the deep source drain regions in the substrate; then providing a dopant through the exposed top surface of the substrate to create the shallow source extensions and the shallow drain extensions.

Claim 20

Dependent Claim 142 words

A process for forming shallow source extensions and shallow drain extensions on a substrate, the process comprising: forming a plurality of gate structures on a top surface of the substrate, each gate structure including a single pair of spacers; forming deep source drain regions on each side of the gate structures, the deep source drain regions not including the shallow source extensions and the shallow drain extensions; siliciding the deep source drain regions; removing the single pair of spacers from each gate structure, thereby exposing the top surface of the substrate; and implanting silicon or germanium through the exposed top surface of the substrate to form amorphous silicon regions exclusive of the deep source drain regions in the substrate; then providing a dopant through the exposed top surface of the substrate to create the shallow source extensions and the shallow drain extensions.

Claim 21

Dependent Claim 18 words

The process of claim 17 , further comprising: activating a dopant at a temperature 600° C. or below.

Claim 22

Dependent Claim 11 words

The process of claim 18 , wherein the siliciding includes nickel.

Claim 23

Dependent Claim 17 words

The process of claim 19 , wherein the energy of the implanting step less than 50 KeV.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2004-02-06	2004-08-07	2005-02-06	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2008-02-06	2008-08-07	2009-02-06	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2012-02-06	2012-08-07	2013-02-06	$7700.00	Window Closed / Lapsed

Process for forming ultra-shallow source/drain extensions

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