Common buffer for multiple streams and control registers in an MPEG-2 compliant transport register

Claim 2

In a transport demultiplexor, a method of decoding a time-division multiplexed bitstream containing packets of audio, video, and system data, where each packet has a packet header, and packet data bytes, said method comprising demultiplexing the bitstream into separate audio and video data bitstreams for decompression while maintaining synchronization, attaching an information word to at least some audio, video and system data packets, loading the demultiplexed system data and the demultiplexed audio and video data packets and their attached information words into a single logical buffer, wherein the system data, the audio data and the video data packets are stored intermixed in the single logical buffer of the transport demultiplexor, unloading the system data and the audio and video data packets from the single logical buffer using the attached information words, and decoding the audio and video data bitstreams in accordance with the system data using audio and video decoders.

Claim 3

The method of claim 1 wherein said single logical buffer is implemented within a packet buffer, said packet buffer further comprising registers, and wherein said method further comprises storing control and status information in said registers of said packet buffer.

Claim 4

The method of claim 1 comprising removing data from the single logical buffer through separate system, audio and video unloaders.

Claim 5

The method of claim 1 comprising storing the system data, the audio data and the video data packets intermixed in said single logical buffer on a packet basis.

Claim 6

The method of claim 1 comprising transferring the system, audio, and video data packets and the control or information words associated with each packet from the single logical buffer through separate system, audio, and video unloaders.

Claim 7

In a transport demultiplexor, a method of decoding a time division multiplexed bitstream containing packets of audio, video, and system data, where each packet has a packet header, and packet data bytes, comprising demultiplexing the bitstream into separate audio and video bitstreams for decompression while maintaining synchronization, loading the system data, the audio data and the video data packets into memory, unloading the system data, the audio data and the video data packets from the memory, and decoding the audio and video bitstreams in accordance with the system data, the improvement comprising: a) prior to said loading, attaching an information word to at least some audio, video and system data Packets; b) storing the system data, the audio data and the video data packets and their attached information words on a packet basis intermixed in a single logical buffer, including storing system data, and video and audio headers in registers in the single logical buffer; and c) wherein said unloading comprises using the attached information words in unloading and transferring the system, audio, and video data packets from the single logical buffer through separate system, audio, and video unloaders to decoders.

Claim 8

In a transport demultiplexor, a method of decoding a time division multiplexed bitstream containing packets of audio, video, and system data, where each packet has a packet header, and packet data bytes, comprising demultiplexing the bitstream into separate audio and video bitstreams for decompression while maintaining synchronization, loading the system data, the audio data and the video data packets into memory, unloading the system data, the audio data and the video data packets from the memory, and decoding the audio and video bitstreams in accordance with the system data, the improvement comprising: a) prior to said loading, attaching an information word to at least some audio, video and system data Packets; b) storing the system data, the audio data and the video data packets and their attached information words on a packet basis intermixed in a single logical buffer, including storing system data, and video and audio headers in registers in the single logical buffer; and c) wherein said unloading comprises using the attached information words in unloading and transferring the system, audio, and video data packets from the single logical buffer through separate system, audio, and video unloaders to decoders.

Claim 9

A transport demultiplexor comprising: front end logic for demultiplexing a multiplexed bitstream containing packets of audio, video, and system data and for attaching an information word to at least some audio, video and system data packets, said information words being distinct from packet header data received at said transport demultiplexor with said packets of audio, video and system data; back end logic for buffering said packets of audio, video, and system data and the attached information words intermixed in a single logical buffer; and said back end logic further comprising a system data unloader, an audio data unloader and a video data unloader, each unloader being coupled to said single logical buffer through a buffer controller for removing data from said single logical buffer using said attached information words.

Claim 10

A transport demultiplexor comprising: front end logic for demultiplexing a multiplexed bitstream containing packets of audio, video, and system data and for attaching an information word to at least some audio, video and system data packets, said information words being distinct from packet header data received at said transport demultiplexor with said packets of audio, video and system data; back end logic for buffering said packets of audio, video, and system data and the attached information words intermixed in a single logical buffer; and said back end logic further comprising a system data unloader, an audio data unloader and a video data unloader, each unloader being coupled to said single logical buffer through a buffer controller for removing data from said single logical buffer using said attached information words.

Claim 11

The transport demultiplexor of claim 7 , wherein said single logical buffer is implemented within a packet buffer, said packet buffer further comprising registers, said registers storing control and status information.