US6181002B1
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device having a plurality of semiconductor chips
Assignee: Katana Silicon Technologies LLC
•
Filing: 1999-12-13
•
Granted: 2001-01-30
•
Expires: 2019-12-13
Abstract
Abstract A semiconductor device includes an insulative substrate having a layer of interconnection patterns formed on a chip-side surface and external terminals formed on the opposite surface, and a plurality of semiconductor chips stacked on the chip-side surface of the insulative substrate. In the semiconductor device, among the plurality of semiconductor chips, a semiconductor chip having the largest plan surface area has the greatest thickness.
Inventors
- 👤 Hiroyuki Juso
- 👤 Yoshiki Sota
- 👤 Tomoyo Maruyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 20:02
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/111; H10W74/114; H10W74/117; H10W90/00; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W72/551; H10W72/552; H10W72/5522; H10W72/851; H10W72/874; H10W72/884; H10W72/90; H10W72/921; H10W72/923; H10W90/20; H10W90/291; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/732; H10W90/734; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
76 words
A semiconductor device which comprises: an insulative substrate having a layer of interconnection patterns formed on a chip-side surface thereof and external terminals formed on a surface thereof opposite from the chip-side surface; and a plurality of semiconductor chips stacked on the chip-side surface of the insulative substrate and each electrically connected to corresponding interconnection patterns; wherein, among the plurality of semiconductor chips, a semiconductor chip having the largest plan surface area has the greatest thickness.
Claim 2
Dependent Claim
76 words
A semiconductor device which comprises: an insulative substrate having a layer of interconnection patterns formed on a chip-side surface thereof and external terminals formed on a surface thereof opposite from the chip-side surface; and a plurality of semiconductor chips stacked on the chip-side surface of the insulative substrate and each electrically connected to corresponding interconnection patterns; wherein, among the plurality of semiconductor chips, a semiconductor chip having the largest plan surface area has the greatest thickness.
Claim 3
Dependent Claim
27 words
A semiconductor device according to claim 1 wherein another layer of Interconnection patterns is provided on the surface of the insulative substrate opposite from the chip-side surface.
Claim 4
Dependent Claim
61 words
A semiconductor device according to claim 1 wherein the plurality of semiconductor chips comprise a first semiconductor chip having a certain thickness and a second semiconductor chip having a smaller plan surface area and a smaller thickness than the first semiconductor chip, the first semiconductor chip being located at a lower position and the second semiconductor chip at an upper position.
Claim 5
Dependent Claim
92 words
A semiconductor device according to claim 1 wherein the plurality of semiconductor chips comprise a first semiconductor chip having a certain thickness, a second semiconductor chip having a smaller plan surface area and a smaller thickness than the first semiconductor chip and a third semiconductor chip having a plan surface area smaller than and a thickness equal to or smaller than the second semiconductor chip, the first semiconductor chip being located at a lower position, the second semiconductor chip at a midst position and the third semiconductor chip at an upper position.
Claim 6
Dependent Claim
111 words
A semiconductor device according to claim 1 wherein the plurality of semiconductor chips comprise a first semiconductor chip having a certain thickness, a second semiconductor chip having a smaller plan surface area and a smaller thickness than the first semiconductor chip and a third semiconductor chip having a plan surface area equal to and a thickness equal to or smaller than the second semiconductor chip, the third semiconductor chip being located at a lower position, the first semiconductor chip at a midst position and the second semiconductor chip at an upper position, the third semiconductor chip being connected to an interconnection pattern on the insulative substrate by a flip-chip connection method.
Claim 7
Dependent Claim
80 words
A semiconductor device according to claim 1 wherein the plurality of semiconductor chips comprise a first semiconductor chip having a certain thickness, a second semiconductor chip having a smaller plan surface area and a smaller thickness than the first semiconductor chip, the second semiconductor chip being located at a lower position and the first semiconductor chip at an upper position, the second semiconductor chip being connected to an interconnection pattern on the insulative substrate by a flip-chip type connection method.
Claim 8
Dependent Claim
96 words
A semiconductor device which comprises: an insulative substrate having a layer of interconnection patterns formed on a chip-side surface thereof and external terminals formed on a surface thereof opposite from the chip-side surface; and a plurality of semiconductor chips stacked on the chip-side surface of the insulative substrate and each electrically connected to corresponding interconnection patterns; wherein, a first of said semiconductor chips has a plan surface area larger than a plan surface area of a second of said plurality of semiconductor chips, said first semiconductor chip having a thickness greater than said second semiconductor chip.
Claim 9
Dependent Claim
96 words
A semiconductor device which comprises: an insulative substrate having a layer of interconnection patterns formed on a chip-side surface thereof and external terminals formed on a surface thereof opposite from the chip-side surface; and a plurality of semiconductor chips stacked on the chip-side surface of the insulative substrate and each electrically connected to corresponding interconnection patterns; wherein, a first of said semiconductor chips has a plan surface area larger than a plan surface area of a second of said plurality of semiconductor chips, said first semiconductor chip having a thickness greater than said second semiconductor chip.
Claim 10
Dependent Claim
28 words
A semiconductor device according to claim 7 , wherein another layer of interconnection patterns is provided on the surface of the insulative substrate opposite from the chip-side surface.
Claim 11
Dependent Claim
25 words
A semiconductor device according to claim 7 , wherein said first semiconductor chip is located closer to said chip-side surface than said second semiconductor chip.
Claim 12
Dependent Claim
82 words
A semiconductor device according to claim 7 , wherein the plurality of semiconductor chips further comprises a third semiconductor chip having a plan surface area smaller than and a thickness equal to or smaller than the second semiconductor chip, the first semiconductor chip being located at a lower position, closer to said chip-side surface than said second and third semiconductor chips, the second semiconductor chip being located at a middle position and the third semiconductor chip being located at an upper position.
Claim 13
Dependent Claim
94 words
A semiconductor device according to claim 7 , wherein the plurality of semiconductor chips further comprises a third semiconductor chip having a plan surface area equal to and a thickness equal to or smaller than the second semiconductor chip, the third semiconductor chip being located at a lower position, closest to said chip-side surface, the first semiconductor chip being located at a midst position and the second semiconductor chip being located at an upper position, the third semiconductor chip being connected to an interconnection pattern on the insulative substrate by a flip-chip connection method.
Claim 14
Dependent Claim
55 words
A semiconductor device according to claim 7 , wherein the second semiconductor chip is located at a lower position, closer to said chip-side surface, and the first semiconductor chip is located at an upper position, the second semiconductor chip being connected to an interconnection pattern on the insulative substrate by a flip-chip type connection method.
Claim 15
Dependent Claim
27 words
A semiconductor device according to claim 7 , wherein a thickness ratio of said thicker, first semiconductor chip to said second semiconductor chip is at least 2.
Claim 16
Dependent Claim
27 words
A semiconductor device according to claim 7 , wherein the thickness ratio of the thicker, first semiconductor chip to the second semiconductor chip is at least 3.
Claim 17
Dependent Claim
27 words
A semiconductor device according to claim 7 , wherein the thickness ratio of the thicker, first semiconductor chip to the second semiconductor chip is at least 4.
References Cited (Backward Citations)
US5804004A
Cited
US5861666A
Cited
EP0782191A2
Cited
JPH09186289A
Cited
US5773896A
Cited
US5953588A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-30 | 2004-07-31 | 2005-01-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-30 | 2008-07-31 | 2009-01-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-30 | 2012-07-31 | 2013-01-30 | $7700.00 | Window Closed / Lapsed |