Serial-parallel conversion apparatus

Claim 2

A serial-parallel conversion apparatus comprising N conversion circuits connected in a tree structure, each of said-N conversion circuits having: a separator for dividing a data received from an upper node according to a clock signal supplied as a first clock signal from said upper node, into a plurality of data corresponding to a plurality of terminals, said separator comprising at least first and second memories, said first and second memories for fetching said data at a first and second transient timing respectively, and holding said data for one cycle of said clock signal before outputting said data; and a clock generator for dividing said clock signal and outputting said divided signal as a second clock signal for a lower node.

Claim 3

A serial-parallel conversion apparatus as claimed in claim 1 , wherein said clock generator has a divider circuit for dividing by two said first clock and outputting said divided clock signal as said second clock signal.

Claim 4

A serial-parallel conversion apparatus as claimed in claim 1 , wherein said clock generator has: a divider circuit for dividing by two said first clock signal; and a delay circuit for delaying output of said divided clock signal by a predetermined period of time.

Claim 5

A serial-parallel conversion apparatus as claimed in claim 2 , wherein said divider circuit is a D-type flip-flop using a reverse Q output as a D input.

Claim 6

A serial-parallel conversion apparatus as claimed in claim 1 , wherein said separator includes a master-slave-master type flip-flop and a D-type flip-flop.

Claim 7

A serial-parallel conversion apparatus as claimed in claim 1 further comprising a first conversion circuit and a second conversion circuit for dividing each of the data outputted from said plurality of terminals, according to said second clock signal outputted from said clock generator.

Claim 8

A serial-parallel conversion apparatus, as claimed in claim 6 further comprising: a second clock generator in each of said first and second conversion circuits for further dividing by two said second clock signal and outputting said divided second clock signal as a third clock signal; and four additional conversion circuits of a third to a seventh conversion circuit that are respectively connected to terminals of said first and said second conversion circuits so as to further divide respective input data according to said third clock signal.

Claim 9

A serial-parallel conversion apparatus as claimed in claim 3 , wherein said divider circuit is a D-type flip-flop using a reverse Q output as a D input.

Claim 10

A serial-parallel conversion apparatus comprising a plurality of conversion circuits, each of said conversion circuits comprising: a first memory that fetches an input data at a first transient timing from a first level to a second level of a first clock signal and maintains said data for one cycle of said first clock signal; a second memory that fetches said input data at a second transient timing from said second level to said first level of said first clock signal and maintains said data for one cycle of said first clock signal before outputting said data at a third transient timing from said first level to said second level; and a clock generator for generating a second clock signal changing its level at a timing approximately at the center of a period during which said first and said second memory maintain and output respective data, wherein said plurality of conversion circuits are 2 N in number (N is a power equal to, or more than 2) and connected in a tree structure having log N (log is a logarithm using 2 as the base) stages in such a manner that outputs of respective data demultiplexer circuits of the I-th stage (I is an integer from 1 to log N) are supplied to a following stage so that outputs of respective conversion circuits of the log N-th stage are in parallel.

Claim 11

A serial-parallel conversion apparatus comprising a plurality of conversion circuits, each of said conversion circuits comprising: a first memory that fetches an input data at a first transient timing from a first level to a second level of a first clock signal and maintains said data for one cycle of said first clock signal; a second memory that fetches said input data at a second transient timing from said second level to said first level of said first clock signal and maintains said data for one cycle of said first clock signal before outputting said data at a third transient timing from said first level to said second level; and a clock generator for generating a second clock signal changing its level at a timing approximately at the center of a period during which said first and said second memory maintain and output respective data, wherein said plurality of conversion circuits are 2 N in number (N is a power equal to, or more than 2) and connected in a tree structure having log N (log is a logarithm using 2 as the base) stages in such a manner that outputs of respective data demultiplexer circuits of the I-th stage (I is an integer from 1 to log N) are supplied to a following stage so that outputs of respective conversion circuits of the log N-th stage are in parallel.

Claim 12

A serial-parallel conversion apparatus comprising: a first flip-flop that fetches an input data at a first transient timing from a first level to a second level of a first clock signal supplied from an upper node and maintains said data for one cycle of said first clock signal before outputting said data; a second flip-flop that fetches an input data at a second transient timing from said second level to said first level of said first clock signal and maintains said data for one cycle of said first clock signal before outputting said data; and a clock generator for generating as a clock signal for a lower node a second clock signal changing its level at a timing approximately at the center of a period during which said first and second flip-flops maintain and output respective data.

Claim 13

A serial-parallel conversion apparatus comprising: a first flip-flop that fetches an input data at a first transient timing from a first level to a second level of a first clock signal supplied from an upper node and maintains said data for one cycle of said first clock signal before outputting said data; a second flip-flop that fetches an input data at a second transient timing from said second level to said first level of said first clock signal and maintains said data for one cycle of said first clock signal before outputting said data; and a clock generator for generating as a clock signal for a lower node a second clock signal changing its level at a timing approximately at the center of a period during which said first and second flip-flops maintain and output respective data.

Claim 14

A serial-parallel conversion apparatus as claimed in claim 10 , wherein said clock generator has a divider circuit for dividing by two said first clock signal and a delay circuit for delaying output of said divided clock signal by a predetermined period of time.

Claim 15

A conversion module for use in a serial-parallel conversion apparatus, said conversion module comprising: a first memory that fetches an input data at a first transient timing from a first level to a second level of a first clock signal; a second memory that fetches said input signal at a second transient timing from said second level to said first level of said first clock signal and maintains said data for one cycle of said first clock signal before outputting said data at a third transient timing from said first level to said second level; and a clock generator for generating a second clock signal changing its level at a timing approximately at the center of a period during which said first and said second memory maintain and output respective data.

Claim 16

A conversion module for use in a serial-parallel conversion apparatus, said conversion module comprising: a first memory that fetches an input data at a first transient timing from a first level to a second level of a first clock signal; a second memory that fetches said input signal at a second transient timing from said second level to said first level of said first clock signal and maintains said data for one cycle of said first clock signal before outputting said data at a third transient timing from said first level to said second level; and a clock generator for generating a second clock signal changing its level at a timing approximately at the center of a period during which said first and said second memory maintain and output respective data.

Claim 17

A conversion module as claimed in claim 12 , wherein said clock generator has a divider circuit for dividing by two said first clock signal and outputting said divided signal as said second clock signal.

Claim 18

A conversion module as claimed in claim 12 , wherein said clock generator has a divider circuit for dividing by two said first clock signal and a delay circuit for delaying output of said divided clock signal by a predetermined period of time.

Claim 19

A conversion module as claimed in claim 13 , wherein said divider circuit is a D-type flip-flop using a reverse Q output as a D input.

Claim 20

A conversion module as claimed in claim 12 , wherein said first memory is a D-type flip-flop and said second memory is a master-slave-master type flip-flop.

Claim 21

A conversion module as claimed in claim 12 , wherein said first level is a low level of said clock signal, and said second level is a high level of said first clock signal.

Claim 22

A conversion module as claimed in claim 14 , wherein said divider circuit is a D-type flip-flop using a reverse Q output as a D input.

Claim 25

A method for dividing and outputting data according to claim 19 , wherein said second clock signal is generated at the center of a period during which said input data is maintained and ouptut as D 0 and D 1 .