Serial to parallel conversion apparatus with means to adjust the phase of a plurality of divided clock signals

Claim 1

A serial to parallel conversion apparatus for converting serial data including word boundary indication data indicative of a boundary position of a word into parallel data of m×n bits in units of a word, m and n being integers equal to or greater than 2, said serial to parallel conversion apparatus comprising: first dividing means for dividing a first clock signal into m to produce a second clock signal and adjusting a phase of the second clock signal in accordance with a first phase adjustment signal; first serial to parallel conversion means for converting the serial data into parallel data of m bits in response to the second clock signal; m storage means each including a plurality of storage sections connected in series for receiving and storing different bits of the parallel data and successively shifting the stored bits in response to the second clock signal; second dividing means for dividing the first clock signal into m×n to produce a third clock signal and adjusting a phase of the third clock signal in accordance with a second phase adjustment signal; detection means for detecting the word boundary indication data based on outputs of said storage sections of said m storage means and producing the first phase adjustment signal and the second phase adjustment signal; and m second serial to parallel conversion means for receiving the different bits of the parallel data of m bits outputted from the last stage ones of said storage sections of said m storage means and each producing first parallel data of n bits in response to the third clock signal.