US5561423A
Expired / Lapsed
US
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Serial to parallel conversion circuit
Assignee: NEC Corp
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Filing: 1994-06-16
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Granted: 1996-10-01
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Expires: 2014-06-16
Abstract
Abstract The invention realizes a serial to parallel conversion circuit which operates at a high speed with low power dissipation. High speed serial data are input and re-timed with a high speed clock input by a first high speed flip-flop. Differential divide-by-eight clock signals are produced by dividing the high speed differential clock input by two using a second high speed flip-flop and are supplied to ninth through eleventh flip-flops, by which divide-by-eight shift clock signals and another series of divide-by-eight shift clocks leading the divide-by-two clocks by a half-period are produced. The output of the first high speed flip-flop is input to a shift register comprising first through fourth flip-flops, and is shifted with the positive phase divide-by-two clock signals. The output of the shift register is then re-timed with the other divide-by-eight shift clock signals described above by twelfth through fifteenth flip-flops. Similarly, the output of the first high speed flip-flop is shifted with the negative phase two-division clocks by fifth through eighth flip-flops and is re-timed with the divide-by-eight clocks by sixteenth through nineteenth flip-flops. The outputs of the twelfth through nineteenth flip-flops serve as outputs of the serial to parallel conversion circuit.
Inventors
- 👤 Shigeki Morisaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 08:18
CPC Classifications
H; H03; H03M; H03M9/00
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
488 words
A serial to parallel conversion circuit, comprising: a first high speed flip-flop having a pair of differential signal input terminals and a pair of differential clock input terminals connected in positive phase connection to a pair of differential data input terminals and a pair of differential clock input terminals of said serial to parallel conversion circuit, respectively; a divide-by-two circuit including a second high speed flip-flop having a pair of differential signal input terminals and a pair of differential clock input terminals connected in negative phase connection to a pair of differential signal output terminals therefrom and said differential clock input terminals of said serial to parallel conversion circuit, respectively; a pair of shift registers having four-stage cascade connection constructions of first through fourth medium speed flip-flops and fifth through eighth medium speed flip-flops, respectively, with each cascade of flip-flops connected so that a signal input terminal of the medium speed flip-flop at the first stage is connected to a positive phase signal output terminal of said first high speed flip-flop, wherein a Q signal output terminal of the medium speed flip-flop at each stage is connected to a signal input terminal of the medium speed flip-flop at the next stage, and wherein the clock input terminals of said first through fourth medium speed flip-flops and the clock input terminals of said fifth through eighth medium speed flip-flops are connected to the positive phase signal output terminal and the negative phase signal output terminal of said second high speed flip-flop, respectively; a divide-by-four circuit including ninth and tenth medium speed flip-flops connected so that a signal input terminal and a Q signal output terminal of said ninth medium speed flip-flop are connected to a Q signal output terminal and a signal input terminal of said tenth medium speed flip-flop, respectively, and clock input terminals of said ninth and tenth medium speed flip-flops are both connected to the positive phase signal output terminal of said second high speed flip-flop; an eleventh medium speed flip-flop having a signal input terminal connected to the Q signal output terminal of said tenth medium speed flip-flop and having a clock input terminal connected to the negative phase signal output terminal of said second high speed flip-flop; and twelfth through fifteenth medium speed flip-flops having signal input terminals connected to the Q signal output terminals of said first through fourth medium speed flip-flops, respectively, and having clock input terminals connected to a Q signal output terminal of said eleventh medium speed flip-flop; sixteenth through nineteenth medium speed flip-flops having signal input terminals connected to the Q signal output terminals of said fifth through eighth medium speed flip-flops, respectively, and having clock input terminals connected to the Q signal output terminal of said ninth medium speed flip-flop, wherein Q signal output terminals of said twelfth through nineteenth medium speed flip-flops are connected to respective parallel signal output terminals of said serial to parallel conversion circuit.
Claim 2
Dependent Claim
488 words
A serial to parallel conversion circuit, comprising: a first high speed flip-flop having a pair of differential signal input terminals and a pair of differential clock input terminals connected in positive phase connection to a pair of differential data input terminals and a pair of differential clock input terminals of said serial to parallel conversion circuit, respectively; a divide-by-two circuit including a second high speed flip-flop having a pair of differential signal input terminals and a pair of differential clock input terminals connected in negative phase connection to a pair of differential signal output terminals therefrom and said differential clock input terminals of said serial to parallel conversion circuit, respectively; a pair of shift registers having four-stage cascade connection constructions of first through fourth medium speed flip-flops and fifth through eighth medium speed flip-flops, respectively, with each cascade of flip-flops connected so that a signal input terminal of the medium speed flip-flop at the first stage is connected to a positive phase signal output terminal of said first high speed flip-flop, wherein a Q signal output terminal of the medium speed flip-flop at each stage is connected to a signal input terminal of the medium speed flip-flop at the next stage, and wherein the clock input terminals of said first through fourth medium speed flip-flops and the clock input terminals of said fifth through eighth medium speed flip-flops are connected to the positive phase signal output terminal and the negative phase signal output terminal of said second high speed flip-flop, respectively; a divide-by-four circuit including ninth and tenth medium speed flip-flops connected so that a signal input terminal and a Q signal output terminal of said ninth medium speed flip-flop are connected to a Q signal output terminal and a signal input terminal of said tenth medium speed flip-flop, respectively, and clock input terminals of said ninth and tenth medium speed flip-flops are both connected to the positive phase signal output terminal of said second high speed flip-flop; an eleventh medium speed flip-flop having a signal input terminal connected to the Q signal output terminal of said tenth medium speed flip-flop and having a clock input terminal connected to the negative phase signal output terminal of said second high speed flip-flop; and twelfth through fifteenth medium speed flip-flops having signal input terminals connected to the Q signal output terminals of said first through fourth medium speed flip-flops, respectively, and having clock input terminals connected to a Q signal output terminal of said eleventh medium speed flip-flop; sixteenth through nineteenth medium speed flip-flops having signal input terminals connected to the Q signal output terminals of said fifth through eighth medium speed flip-flops, respectively, and having clock input terminals connected to the Q signal output terminal of said ninth medium speed flip-flop, wherein Q signal output terminals of said twelfth through nineteenth medium speed flip-flops are connected to respective parallel signal output terminals of said serial to parallel conversion circuit.
Claim 3
Dependent Claim
39 words
A serial to parallel conversion circuit as claimed in claim 1, wherein each of the high speed flip-flops has a gate of the NMOS type and an active load and performs the same logical operation as a D-type flip-flop.
Claim 4
Dependent Claim
22 words
A serial to parallel conversion circuit as claimed in claim 1, wherein each of the medium speed flip-flops is a D-type flip-flop.
References Cited (Backward Citations)
US5155487A
Cited
US5223833A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-01 | 2000-04-01 | 2000-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-01 | 2004-04-01 | 2004-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-01 | 2008-04-01 | 2008-10-01 | $7700.00 | Window Closed / Lapsed |