Patent US6172422B1 successfully refreshed from Google Patents.
US6172422B1
Expired / Lapsed
US
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Semiconductor device and a manufacturing method thereof
Assignee: PFU Ltd
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Filing: 1998-10-14
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Granted: 2001-01-09
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Expires: 2018-10-14
Abstract
Abstract A manufacturing method of a semiconductor device for mounting an LSI bare-chip component, or a bare chip, on a printed circuit board, or a substrate, with flip-chip bonding technology, comprises a recess forming step of forming recesses on substrate pads of the substrate, an adhesive coating step of applying adhesive to a location on the substrate at which the bare chip is to be placed, a chip mounting step of placing the bare chip on the substrate while aligning the positions of the bumps formed on the chip pads of the bare chip and the substrate pads of the substrate, and an adhesive hardening step of hardening the applied adhesive. Also disclosed is a semiconductor device manufactured with the above-mentioned manufacturing method.
Inventors
- 👤 Yasuhide Chigawa
- 👤 Ippei Fujiyama
- 👤 Kenji Matsuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 17:01
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W72/00; H10W72/30; H10W74/00; H10W74/01; H10W74/012; H10W74/10; H10W74/15; H10W70/681; H10W72/01; H10W72/012; H10W72/01221; H10W72/01225; H10W72/071; H10W72/072; H10W72/073; H10W72/20; H10W72/241; H10W72/251; H10W72/252; H10W72/50; H10W72/551; H10W72/552; H10W72/5522; H10W72/851; H10W72/853; H10W72/856; H10W90/00; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/734
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
124 words
A semiconductor device, comprising: a substrate including recessed portions in a surface thereof; a plurality of substrate pads formed directly on said substrate and including recessed portions corresponding to the respective recessed portions in the surface of the substrate; a plurality of bumps positioned on said recessed portions of said respective substrate pads; a bare chip adhesively bonded to said surface of said substrate, said bare chip including a plurality of chip pads electrically connected to said substrate pads, wherein said plurality of chip pads are located at respective positions corresponding to said respective recessed portions of the substrate pads, and wherein said respective recessed portions of said substrate pads and said respective recessed portion of said substrate are formed by a pushing force.
Claim 2
Dependent Claim
124 words
A semiconductor device, comprising: a substrate including recessed portions in a surface thereof; a plurality of substrate pads formed directly on said substrate and including recessed portions corresponding to the respective recessed portions in the surface of the substrate; a plurality of bumps positioned on said recessed portions of said respective substrate pads; a bare chip adhesively bonded to said surface of said substrate, said bare chip including a plurality of chip pads electrically connected to said substrate pads, wherein said plurality of chip pads are located at respective positions corresponding to said respective recessed portions of the substrate pads, and wherein said respective recessed portions of said substrate pads and said respective recessed portion of said substrate are formed by a pushing force.
Claim 3
Dependent Claim
18 words
A semiconductor device according to claim 1 , wherein said substrate comprises a material having high elastic deformability.
Claim 4
Dependent Claim
15 words
A semiconductor device according to claim 1 wherein said adhesive does not include a void.
Claim 5
Dependent Claim
20 words
A semiconductor device according to claim 1 , wherein a surface of said substrate pads of said substrate is roughened.
Claim 6
Dependent Claim
26 words
A semiconductor device according to claim 1 , wherein a height of said bumps is set to a level beyond which no further deformation is caused.
Claim 7
Dependent Claim
100 words
A semiconductor device, comprising: a substrate including recessed portions in a surface thereof; a plurality of substrate pads formed directly on said substrate and including recessed portions corresponding to the respective recessed portions in the surface of the substrate; a plurality of bumps positioned on said recessed portions of said respective substrate pads; a bare chip adhesively bonded to said surface of said substrate, said bare chip including a plurality of chip pads electrically connected to said substrate pads, wherein said plurality of chip pads are located at respective positions corresponding to said respective recessed portions of the substrate pads.
Claim 8
Dependent Claim
100 words
A semiconductor device, comprising: a substrate including recessed portions in a surface thereof; a plurality of substrate pads formed directly on said substrate and including recessed portions corresponding to the respective recessed portions in the surface of the substrate; a plurality of bumps positioned on said recessed portions of said respective substrate pads; a bare chip adhesively bonded to said surface of said substrate, said bare chip including a plurality of chip pads electrically connected to said substrate pads, wherein said plurality of chip pads are located at respective positions corresponding to said respective recessed portions of the substrate pads.
Claim 9
Dependent Claim
18 words
A semiconductor device according to claim 6 , wherein said substrate comprises a material having high elastic deformability.
Claim 10
Dependent Claim
16 words
A semiconductor device according to claim 6 , wherein said adhesive does not include a void.
Claim 11
Dependent Claim
20 words
A semiconductor device according to claim 6 , wherein a surface of said substrate pads of said substrate is roughened.
Claim 12
Dependent Claim
22 words
A semiconductor device according to claim 6 , wherein the recessed amount of said substrate pads is set at a predetermined value.
Claim 13
Dependent Claim
26 words
A semiconductor device according to claim 6 , wherein a height of said bumps is set to a level beyond which no further deformation is caused.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-01-09 | 2004-07-10 | 2005-01-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-01-09 | 2008-07-10 | 2009-01-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-01-09 | 2012-07-10 | 2013-01-09 | $7700.00 | Window Closed / Lapsed |