Patent FR1028247A successfully refreshed from Google Patents.
US5801447A
Expired / Lapsed
US
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Flip chip mounting type semiconductor device
Assignee: Toshiba Corp
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Filing: 1996-04-24
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Granted: 1998-09-01
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Expires: 2016-04-24
Abstract
Abstract In a flip chip mounting type semiconductor device, on a corner portion of a chip subjected to flip chip mounting, a gate region for injecting a sealing member filled between a mounted board and the chip is arranged. In this semiconductor device, a semiconductor element has a plurality of bumps formed on the peripheral portion on a major surface along each side, a plurality of pad electrodes are formed on the major surface of the circuit board, and the pad electrodes join the bumps. A resin sealing member is filled between the semiconductor element and the circuit board. A gate region through which the resin sealing member is injected is formed on a corner portion of the semiconductor element. In the gate region, no bump is formed, or bumps are arranged at intervals smaller than that in another region. For this reason, the resin uniformly enters the space between the semiconductor element and the circuit board through the gate region.
Inventors
- 👤 Naohiko Hirano
- 👤 Kazuhide Doi
- 👤 Chiaki Takubo
- 👤 Hiroshi Tazawa
- 👤 Eiichi Hosomi
- 👤 Yoichi Hiruta
- 👤 Takashi Okada
- 👤 Koji Shibasaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 11:22
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/65; H10W74/00; H10W74/01; H10W74/012; H10W74/10; H10W74/15; H10W70/67; H10W70/68; H10W70/681; H10W72/00; H10W72/071; H10W72/072; H10W72/073; H10W72/20; H10W72/241; H10W72/247; H10W72/248; H10W72/30; H10W72/351; H10W72/352; H10W72/353; H10W72/354; H10W72/851; H10W72/853; H10W72/856; H10W90/00; H10W90/701; H10W90/721; H10W90/724; H10W90/731; H10W90/734
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
131 words
A semiconductor device comprising: a semiconductor element having a plurality of projection electrodes formed along each side of a peripheral portion on a major surface; a circuit board having a major surface on which a plurality of pad electrodes are formed, said pad electrodes joining said projection electrodes of said semiconductor element; and a sealing member filled between said semiconductor element and said circuit board; wherein a gate region in which said sealing member is injected is formed on a corner portion of said semiconductor element, and wherein said plurality of projection electrodes are arranged at predetermined intervals on the major surface of said semiconductor element, and the predetermined interval of the projection electrodes in said gate region is larger than the predetermined interval of the projection electrodes in another region.
Claim 2
Dependent Claim
131 words
A semiconductor device comprising: a semiconductor element having a plurality of projection electrodes formed along each side of a peripheral portion on a major surface; a circuit board having a major surface on which a plurality of pad electrodes are formed, said pad electrodes joining said projection electrodes of said semiconductor element; and a sealing member filled between said semiconductor element and said circuit board; wherein a gate region in which said sealing member is injected is formed on a corner portion of said semiconductor element, and wherein said plurality of projection electrodes are arranged at predetermined intervals on the major surface of said semiconductor element, and the predetermined interval of the projection electrodes in said gate region is larger than the predetermined interval of the projection electrodes in another region.
Claim 3
Dependent Claim
31 words
A semiconductor device according to claim 1, wherein the shape of said gate region is a square or rectangular shape having two adjacent sides constituting a corner of said semiconductor element.
Claim 4
Dependent Claim
19 words
A semiconductor device according to claim 2, wherein said plurality of projection electrodes are arranged in a staggered form.
Claim 5
Dependent Claim
58 words
A semiconductor device according to claim 1, wherein said projection electrodes are arranged in two arrays along each side of the peripheral portion on the major surface, intervals between the projection electrodes arranged in the inner array of the two arrays being larger than intervals between the projection electrodes arranged in the outer array of the two arrays.
Claim 6
Dependent Claim
44 words
A semiconductor device according to claim 1, wherein said projection electrodes are arranged in two arrays along each side of the peripheral portion on the major surface, selected ones of the projection electrodes arranged in the inner array of the two arrays being removed.
References Cited (Backward Citations)
US4021838A
Cited
US5647123A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-31 | 2002-03-02 | 2002-09-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-31 | 2006-03-02 | 2006-09-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-31 | 2010-03-02 | 2010-09-01 | $7700.00 | Window Closed / Lapsed |