Offset-compensated switched-opamp integrator and filter

Claim 2

An integrator which operates under a low power voltage and provides compensation for offset voltages, the integrator comprising: a first amplifier having a non-inverting input terminal coupled to a ground, an inverting input terminal, and an output terminal; a fifth capacitor coupled to said inverting input terminal of said first amplifier; a first capacitor, which has a first terminal coupled to said fifth capacitor and a second terminal receiving an input signal; a first switch coupled between said second terminal of said first capacitor and said ground; a second switch coupled between said ground and a terminal coupling said first capacitor and said fifth capacitor; a third switch coupled to said terminal coupling, said first capacitor, and said fifth capacitor; a second capacitor coupled between said third switch and said output terminal of said first amplifier; a fourth switch coupled between said inverting input terminal and said output terminal of said first amplifier; a third capacitor coupled to said output terminal of said first amplifier; a second amplifier comprising a non-inverting input terminal coupled to said ground, an inverting input terminal coupled to said third capacitor (three capacitors), and an output terminal; and a fourth capacitor and a fifth switch coupled in parallel between said inverting input terminal and said output terminal of said second amplifier.

Claim 3

The integrator of claim 1 wherein a first timing waveform operates said first, second and fourth switches and a second timing waveform operates said third switch and fifth switch, said first and second timing waveforms having a same period and showing different logic levels at the same time.

Claim 4

A filter which operates under a low power voltage and provides compensation for offset voltages the filter, comprising: a first amplifier having a non-inverting input terminal coupled to a ground, an inverting input terminal, and an output terminal; a first capacitor coupled to said inverting input terminal of said first amplifier; a first switch coupled between said first capacitor and a signal input terminal; a second switch coupled between said ground and a terminal coupling said first capacitor and said first switch; a second capacitor coupled to said output terminal of said first amplifier; a third switch coupled between said inverting input terminal of said first amplifier and said second capacitor; a fourth switch coupled between said output terminal and said inverting input terminal of said first amplifier; a third capacitor coupled to said output terminal of said first amplifier; a second amplifier having a non-inverting input terminal coupled to a ground, an inverting input terminal coupled to said third capacitor, and an output terminal; a fourth capacitor and a fifth switch coupled in parallel between said inverting input terminal and said output terminal of said second amplifier; a fifth capacitor coupled to said output terminal of said second amplifier; a seventh switch coupled to said fifth capacitor; a sixth switch coupled between said inverting terminal of said second amplifier and a terminal coupling said fifth capacitor and said seventh switch; a ninth capacitor coupled to said seventh switch; an eighth switch coupled between said ground and a terminal coupling said seventh switch and said ninth capacitor; a third amplifier having a non-inverting input terminal coupled to a ground, an inverting input terminal coupled to said ninth capacitor, and an output terminal; a ninth switch coupled between said inverting input terminal and said output terminal of said third amplifier; a tenth switch and an eleventh switch coupled in parallel to a terminal coupling said ninth capacitor and said seventh switch; a six capacitor coupled between said tenth switch and said output terminal of said third amplifier; a seventh capacitor coupled between said eleventh switch and said output terminal of said third amplifier; a twelfth switch coupled between said inverting input terminal of said third amplifier and a terminal coupling said eleventh switch and said seventh capacitor; an eighth capacitor coupled to said output terminal of said third amplifier; a thirteenth switch coupled between said eighth capacitor and said ground; and a fourteenth switch coupled to said inverting input terminal of said first amplifier and a terminal coupling said eighth capacitor and said thirteenth switch.

Claim 5

A filter which operates under a low power voltage and provides compensation for offset voltages the filter, comprising: a first amplifier having a non-inverting input terminal coupled to a ground, an inverting input terminal, and an output terminal; a first capacitor coupled to said inverting input terminal of said first amplifier; a first switch coupled between said first capacitor and a signal input terminal; a second switch coupled between said ground and a terminal coupling said first capacitor and said first switch; a second capacitor coupled to said output terminal of said first amplifier; a third switch coupled between said inverting input terminal of said first amplifier and said second capacitor; a fourth switch coupled between said output terminal and said inverting input terminal of said first amplifier; a third capacitor coupled to said output terminal of said first amplifier; a second amplifier having a non-inverting input terminal coupled to a ground, an inverting input terminal coupled to said third capacitor, and an output terminal; a fourth capacitor and a fifth switch coupled in parallel between said inverting input terminal and said output terminal of said second amplifier; a fifth capacitor coupled to said output terminal of said second amplifier; a seventh switch coupled to said fifth capacitor; a sixth switch coupled between said inverting terminal of said second amplifier and a terminal coupling said fifth capacitor and said seventh switch; a ninth capacitor coupled to said seventh switch; an eighth switch coupled between said ground and a terminal coupling said seventh switch and said ninth capacitor; a third amplifier having a non-inverting input terminal coupled to a ground, an inverting input terminal coupled to said ninth capacitor, and an output terminal; a ninth switch coupled between said inverting input terminal and said output terminal of said third amplifier; a tenth switch and an eleventh switch coupled in parallel to a terminal coupling said ninth capacitor and said seventh switch; a six capacitor coupled between said tenth switch and said output terminal of said third amplifier; a seventh capacitor coupled between said eleventh switch and said output terminal of said third amplifier; a twelfth switch coupled between said inverting input terminal of said third amplifier and a terminal coupling said eleventh switch and said seventh capacitor; an eighth capacitor coupled to said output terminal of said third amplifier; a thirteenth switch coupled between said eighth capacitor and said ground; and a fourteenth switch coupled to said inverting input terminal of said first amplifier and a terminal coupling said eighth capacitor and said thirteenth switch.

Claim 6

The filter of claim 3 , wherein a first timing waveform operates said second, third, fifth, sixth, eighth, ninth, eleventh, twelfth, and fourteenth switches and a second timing waveform operates said first, fourth, seventh, tenth, and thirteenth switch, said first and second timing waveforms having a same period and showing different logic levels at the same time.