Patent US6166955A successfully refreshed from Google Patents.
US6166955A
Expired / Lapsed
US
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Apparatus and method for programming of flash EPROM memory
Assignee: Macronix International Co Ltd
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Filing: 1999-07-09
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Granted: 2000-12-26
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Expires: 2019-07-09
Abstract
Abstract An apparatus for programming selected floating gate storage transistors in a data storage device includes a voltage supply circuit, coupled to the control gate and the source of a selected floating gate storage transistor, to supply a gate programming potential across the control gate and the source to move charge in the floating gate. Circuitry, coupled to the selected floating gate storage transistor, maintains drain current of the selected floating gate transistor at a substantially stable value during programming. In one example, the circuitry is a stable current source in parallel with a load coupled to the source of the selected floating gate transistor. The stable current source, in one embodiment, is a current mirror designed to supply a fixed current level. The load may be a resistor chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited. The load may be a diode chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited.
Inventors
- 👤 Wenpin Lu
- 👤 Ming-Shang Chen
- 👤 Mam-Tsung Wang
- 👤 Baw-Chyuan Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 14:58
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; G11C16/06; G11C16/10; G11C16/12
Claims Analysis
Total Claims: 46
Claim 1
Independent Claim
101 words
In a data storage device including a plurality of floating gate storage transistors having respective control gates, sources, and drains, an apparatus for programming selected floating gate storage transistors, the apparatus comprising: a voltage supply circuit, coupled to the control gate and the source of a selected floating gate storage transistor, to supply a gate programming potential across the control gate and the source to move charge in the floating gate; and circuitry, coupled to the selected floating gate storage transistor, the circuitry selected to maintain drain current of the selected floating gate transistor at a substantially stable value during programming.
Claim 2
Dependent Claim
101 words
In a data storage device including a plurality of floating gate storage transistors having respective control gates, sources, and drains, an apparatus for programming selected floating gate storage transistors, the apparatus comprising: a voltage supply circuit, coupled to the control gate and the source of a selected floating gate storage transistor, to supply a gate programming potential across the control gate and the source to move charge in the floating gate; and circuitry, coupled to the selected floating gate storage transistor, the circuitry selected to maintain drain current of the selected floating gate transistor at a substantially stable value during programming.
Claim 3
Dependent Claim
128 words
In a data storage device including a plurality of floating gate storage transistors having respective control gates, sources, and drains, an apparatus for programming selected floating gate storage transistors, the apparatus comprising: a voltage supply circuit, coupled to the control gate and the source of a selected floating gate storage transistor, to supply a gate programming potential across the control gate and the source to move charge in the floating gate; and circuitry, coupled to the selected floating gate storage transistor, the circuitry selected to maintain drain current of the selected floating gate transistor at a substantially stable value during programming, wherein the circuitry comprises a stable current source in parallel with a load, the stable current source coupled to the source of the selected floating gate transistor.
Claim 4
Dependent Claim
128 words
In a data storage device including a plurality of floating gate storage transistors having respective control gates, sources, and drains, an apparatus for programming selected floating gate storage transistors, the apparatus comprising: a voltage supply circuit, coupled to the control gate and the source of a selected floating gate storage transistor, to supply a gate programming potential across the control gate and the source to move charge in the floating gate; and circuitry, coupled to the selected floating gate storage transistor, the circuitry selected to maintain drain current of the selected floating gate transistor at a substantially stable value during programming, wherein the circuitry comprises a stable current source in parallel with a load, the stable current source coupled to the source of the selected floating gate transistor.
Claim 5
Dependent Claim
34 words
The apparatus of claim 2, wherein the stable current source comprises a current mirror designed to supply a fixed current level, the current mirror coupled to the source of the selected floating gate transistor.
Claim 6
Dependent Claim
14 words
The apparatus of claim 2, wherein the stable current source comprises a MOS device.
Claim 7
Dependent Claim
32 words
The apparatus of claim 2, wherein the load comprises a resistor chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited.
Claim 8
Dependent Claim
32 words
The apparatus of claim 2, wherein the load comprises a diode chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited.
Claim 9
Dependent Claim
31 words
The apparatus of claim 1, wherein a substrate of the selected floating gate storage transistor is biased at a negative voltage, allowing control gate voltage and drain voltage to be reduced.
Claim 10
Dependent Claim
24 words
The apparatus of claim 1, including control circuitry coupled to the voltage supply circuit to vary the gate programming potential during a programming interval.
Claim 11
Dependent Claim
30 words
The apparatus of claim 8, wherein a rate of varying the gate programming potential is chosen to improve gate injection efficiency for a cell with a relatively low threshold voltage.
Claim 12
Dependent Claim
17 words
The apparatus of claim 1, wherein the floating gate storage transistor comprises a non-split floating gate transistor.
Claim 13
Dependent Claim
107 words
In a data storage device including a plurality of floating gate storage transistors having respective control gates, sources, and drains, an apparatus for programming selected floating gate storage transistors, the apparatus comprising: a voltage supply circuit, coupled to the control gate and the source of a selected floating gate storage transistor, to supply a gate programming potential across the control gate and the source to move charge in the floating gate; and a bias component, coupled to the source of the selected floating gate storage transistor, the bias component selected to supply less source current at lower source bias and more source current at higher source bias.
Claim 14
Dependent Claim
107 words
In a data storage device including a plurality of floating gate storage transistors having respective control gates, sources, and drains, an apparatus for programming selected floating gate storage transistors, the apparatus comprising: a voltage supply circuit, coupled to the control gate and the source of a selected floating gate storage transistor, to supply a gate programming potential across the control gate and the source to move charge in the floating gate; and a bias component, coupled to the source of the selected floating gate storage transistor, the bias component selected to supply less source current at lower source bias and more source current at higher source bias.
Claim 15
Dependent Claim
121 words
In a data storage device including a plurality of floating gate storage transistors having respective control gates, sources, and drains, an apparatus for programming selected floating gate storage transistors, the apparatus comprising: a voltage supply circuit, coupled to the control gate and the source of a selected floating gate storage transistor, to supply a gate programming potential across the control gate and the source to move charge in the floating gate; and a bias component, coupled to the source of the selected floating gate storage transistor, the bias component selected to supply less source current at lower source bias and more source current at higher source bias, wherein the bias component comprises a stable current source in parallel with a load.
Claim 16
Dependent Claim
121 words
In a data storage device including a plurality of floating gate storage transistors having respective control gates, sources, and drains, an apparatus for programming selected floating gate storage transistors, the apparatus comprising: a voltage supply circuit, coupled to the control gate and the source of a selected floating gate storage transistor, to supply a gate programming potential across the control gate and the source to move charge in the floating gate; and a bias component, coupled to the source of the selected floating gate storage transistor, the bias component selected to supply less source current at lower source bias and more source current at higher source bias, wherein the bias component comprises a stable current source in parallel with a load.
Claim 17
Dependent Claim
21 words
The apparatus of claim 12, wherein the stable current source comprises a current mirror designed to supply a fixed current level.
Claim 18
Dependent Claim
14 words
The apparatus of claim 12, wherein the stable current source comprises a MOS device.
Claim 19
Dependent Claim
32 words
The apparatus of claim 12, wherein the load comprises a resistor chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited.
Claim 20
Dependent Claim
32 words
The apparatus of claim 12, wherein the load comprises a diode chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited.
Claim 21
Dependent Claim
31 words
The apparatus of claim 11, wherein a substrate of the selected floating gate storage transistor is biased at a negative voltage, allowing control gate voltage and drain voltage to be reduced.
Claim 22
Dependent Claim
24 words
The apparatus of claim 11, including control circuitry coupled to the voltage supply circuit to vary the gate programming potential during a programming interval.
Claim 23
Dependent Claim
30 words
The apparatus of claim 18, wherein a rate of varying the gate programming potential is chosen to improve gate injection efficiency for a cell with a relatively low threshold voltage.
Claim 24
Dependent Claim
17 words
The apparatus of claim 11, wherein the floating gate storage transistor comprises a non-split floating gate transistor.
Claim 25
Dependent Claim
111 words
An integrated circuit memory, comprising: a memory array of flash EPROM memory cells having control gates, floating gates, sources and drains; a plurality of bit lines, each coupled to the drains of a column of cells in the memory array; a plurality of word lines, each coupled to the control gates of a row of cells in the memory array; a plurality of virtual ground terminals, each coupled to the sources of a plurality of blocks of cells in the memory array; and circuitry, coupled to the plurality of virtual ground terminals, the circuitry selected to maintain drain current of a selected memory cell at a substantially stable value during programming.
Claim 26
Dependent Claim
111 words
An integrated circuit memory, comprising: a memory array of flash EPROM memory cells having control gates, floating gates, sources and drains; a plurality of bit lines, each coupled to the drains of a column of cells in the memory array; a plurality of word lines, each coupled to the control gates of a row of cells in the memory array; a plurality of virtual ground terminals, each coupled to the sources of a plurality of blocks of cells in the memory array; and circuitry, coupled to the plurality of virtual ground terminals, the circuitry selected to maintain drain current of a selected memory cell at a substantially stable value during programming.
Claim 27
Dependent Claim
20 words
The integrated circuit memory of claim 21, wherein the circuitry comprises a stable current source in parallel with a load.
Claim 28
Dependent Claim
23 words
The integrated circuit memory of claim 22, wherein the stable current source comprises a current mirror designed to supply a fixed current level.
Claim 29
Dependent Claim
16 words
The integrated circuit memory of claim 22, wherein the stable current source comprises a MOS device.
Claim 30
Dependent Claim
34 words
The integrated circuit memory of claim 22, wherein the load comprises a resistor chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited.
Claim 31
Dependent Claim
34 words
The integrated circuit memory of claim 22, wherein the load comprises a diode chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited.
Claim 32
Dependent Claim
29 words
The integrated circuit memory of claim 21, wherein a substrate of the cells is biased at a negative voltage, allowing control gate voltage and drain voltage to be reduced.
Claim 33
Dependent Claim
26 words
The integrated circuit memory of claim 21, including control circuitry coupled to the voltage supply circuit to vary the gate programming potential during a programming interval.
Claim 34
Dependent Claim
32 words
The integrated circuit memory of claim 28, wherein a rate of varying the gate programming potential is chosen to improve gate injection efficiency for a cell with a relatively low threshold voltage.
Claim 35
Dependent Claim
15 words
The integrated circuit memory of claim 21, wherein the cells comprise non-split floating gate transistors.
Claim 36
Dependent Claim
67 words
In a data storage device including a plurality of floating gate storage transistors having respective control gates, sources, and drains, a method for programming selected floating gate storage transistors comprising: supplying a gate programming potential across the control gate and the source to move charge in the selected floating gate; and maintaining drain current of the selected floating gate transistor at a substantially stable value during programming.
Claim 37
Dependent Claim
67 words
In a data storage device including a plurality of floating gate storage transistors having respective control gates, sources, and drains, a method for programming selected floating gate storage transistors comprising: supplying a gate programming potential across the control gate and the source to move charge in the selected floating gate; and maintaining drain current of the selected floating gate transistor at a substantially stable value during programming.
Claim 38
Dependent Claim
30 words
The method of claim 31, comprising providing a stable current source in parallel with a load, the stable current source coupled to the source of the selected floating gate transistor.
Claim 39
Dependent Claim
34 words
The method of claim 32, wherein the stable current source comprises a current mirror designed to supply a fixed current level, the current mirror coupled to the source of the selected floating gate transistor.
Claim 40
Dependent Claim
14 words
The method of claim 32, wherein the stable current source comprises a MOS device.
Claim 41
Dependent Claim
32 words
The method of claim 32, wherein the load comprises a resistor chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited.
Claim 42
Dependent Claim
32 words
The method of claim 32, wherein the load comprises a diode chosen to control a slope of a curve of source current versus source voltage such that drain current variation is limited.
Claim 43
Dependent Claim
31 words
The method of claim 31, wherein a substrate of the selected floating gate storage transistor is biased at a negative voltage, allowing control gate voltage and drain voltage to be reduced.
Claim 44
Dependent Claim
15 words
The method of claim 31, including varying the gate programming potential during a programming interval.
Claim 45
Dependent Claim
30 words
The method of claim 38, wherein a rate of varying the gate programming potential is chosen to improve gate injection efficiency for a cell with a relatively low threshold voltage.
Claim 46
Dependent Claim
17 words
The method of claim 21, wherein the floating gate storage transistor comprises a non-split floating gate transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-26 | 2004-06-26 | 2004-12-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-26 | 2008-06-26 | 2008-12-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-26 | 2012-06-26 | 2012-12-26 | $7700.00 | Window Closed / Lapsed |