US5530669A
Expired / Lapsed
US
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Non-volatile semiconductor memory device and method for recovering write characteristics
Assignee: NEC Electronics Corp
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Filing: 1994-10-28
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Granted: 1996-06-25
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Expires: 2014-10-28
Abstract
Abstract In an EEPROM, a substrate is grounded, and a voltage supply voltage (5 V) and a high voltage (12 V) are applied to a drain region and a control gate, respectively, while maintaining a source region in a floating condition, so that a voltage stress is applied to a tunnel gate oxide film. As a result, electrons trapped in the tunnel gate oxide film are extracted to a floating gate. Thus, deterioration of the tunnel gate oxide film which is caused by repetition of write/erase, will be recovered.
Inventors
- 👤 Ken-Ichi Oyama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 03:37
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/344; G11C16/3445; G11C16/10; G11C16/14; G11C16/16; G11C16/349; G11C16/3495
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
155 words
A non-volatile semiconductor memory device including at least one electrically erasable memory cell having a source region, a drain region, and a channel region defined between the source region and the drain region, and a stacked gate structure formed on the channel region and including a first gate insulator film, a floating gate electrode, a second gate insulator film and a control gate electrode stacked on the channel region in the named order, the non-volatile semiconductor memory device comprising: a write mode, a read mode, an erase mode and a stress application mode, in said stress application mode, a high positive voltage is applied to said control gate electrode, an intermediate positive voltage is applied to said drain voltage, and a ground voltage or a negative voltage is applied to a substrate, so that a voltage stress is applied on said first gate insulator film, while maintaining a condition in which no channel current flows.
Claim 2
Dependent Claim
155 words
A non-volatile semiconductor memory device including at least one electrically erasable memory cell having a source region, a drain region, and a channel region defined between the source region and the drain region, and a stacked gate structure formed on the channel region and including a first gate insulator film, a floating gate electrode, a second gate insulator film and a control gate electrode stacked on the channel region in the named order, the non-volatile semiconductor memory device comprising: a write mode, a read mode, an erase mode and a stress application mode, in said stress application mode, a high positive voltage is applied to said control gate electrode, an intermediate positive voltage is applied to said drain voltage, and a ground voltage or a negative voltage is applied to a substrate, so that a voltage stress is applied on said first gate insulator film, while maintaining a condition in which no channel current flows.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-06-25 | 1999-12-25 | 2000-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-06-25 | 2003-12-25 | 2004-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-06-25 | 2007-12-25 | 2008-06-25 | $7700.00 | Window Closed / Lapsed |