US6159795A
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US
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Low voltage junction and high voltage junction optimization for flash memory
Assignee: Monterey Research LLC
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Filing: 1998-07-02
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Granted: 2000-12-12
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Expires: 2018-07-02
Abstract
Abstract An intermediate implant step is performed to optimize the performance of the transistors in the peripheral portion of a floating gate type memory integrated circuit. The polysilicon layer (Poly 1) that forms the floating gate in the respective floating gate type memory devices prevents penetration of the optimizing implant into the core region in which the floating gate memory devices are formed. This permits the optimization implant to be performed without the need for an additional mask, thus reducing costs and production time.
Inventors
- 👤 Masaaki Higashitani
- 👤 Hao Fang
- 👤 Narbeh Derhacobian
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:52
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/49; Y; Y10; Y10S; Y10S438/00; Y10S438/976
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
265 words
A method for manufacturing a floating gate type memory device, comprising the steps of: forming a gate oxide layer on a surface of a substrate in a peripheral region, and forming a tunnel oxide layer on the surface of the substrate in a memory core region; forming a first conductive layer on the tunnel oxide layer to function as a floating gate for a number of transistors to be formed in the memory core region; forming a dielectric layer on the first conductive layer; forming a second conductive layer on the dielectric layer in the memory core region and on the gate oxide layer in the peripheral region; selectively removing a number of portions of the second conductive layer, the dielectric layer, and the gate oxide layer to form at least one gate structure for at least one transistor in the peripheral region and a number of gate structures for the transistors in the memory core region; performing a first implant step to implant a dopant in a source region and in a drain region in the substrate adjacent the at least one gate structure of the at least one transistor in the peripheral region; masking a number of substrate areas adjacent to the gate structures of the transistors to be formed in the memory core region with the first conductive layer during the first implant step; and subsequent to the first implant and masking steps, selectively removing portions of the first conductive layer in the memory core region to define a number of respective floating gates for the transistors in the memory core region.
Claim 2
Independent Claim
265 words
A method for manufacturing a floating gate type memory device, comprising the steps of: forming a gate oxide layer on a surface of a substrate in a peripheral region, and forming a tunnel oxide layer on the surface of the substrate in a memory core region; forming a first conductive layer on the tunnel oxide layer to function as a floating gate for a number of transistors to be formed in the memory core region; forming a dielectric layer on the first conductive layer; forming a second conductive layer on the dielectric layer in the memory core region and on the gate oxide layer in the peripheral region; selectively removing a number of portions of the second conductive layer, the dielectric layer, and the gate oxide layer to form at least one gate structure for at least one transistor in the peripheral region and a number of gate structures for the transistors in the memory core region; performing a first implant step to implant a dopant in a source region and in a drain region in the substrate adjacent the at least one gate structure of the at least one transistor in the peripheral region; masking a number of substrate areas adjacent to the gate structures of the transistors to be formed in the memory core region with the first conductive layer during the first implant step; and subsequent to the first implant and masking steps, selectively removing portions of the first conductive layer in the memory core region to define a number of respective floating gates for the transistors in the memory core region.
Claim 3
Dependent Claim
54 words
The method of claim 1, wherein the peripheral region is to include both a number of high voltage transistors and a number of low voltage transistors, and the first implant step is performed at least with respect to a number of source regions and a number of drain regions of the high voltage transistors.
Claim 4
Dependent Claim
55 words
The method of claim 1, further comprising the step of performing a second implant step to implant a dopant at a higher density into the source region and the drain region of the at least one transistor, the second implant step being performed subsequent the step of selectively removing portions of the first conductive layer.
Claim 5
Dependent Claim
33 words
The method of claim 3, wherein the first implant step further comprises the step of implanting the dopant at a lower dose level and a lower energy level than the second implant step.
Claim 6
Dependent Claim
20 words
The method of claim 1, wherein the first conductive layer and the second conductive layer are each made of polysilicon.
Claim 7
Independent Claim
169 words
A method for optimizing a voltage junction in a transistor included in a floating gate type memory device, comprising the steps of: forming a gate structure for the transistor on a surface of a substrate in a peripheral region of the substrate; forming at least a partial gate structure for each of a plurality of memory transistors on the surface of the substrate in a core region, the partial gate structure including a first conductive layer configured to function as a floating gate in each of the memory transistors; performing an implant step to implant a dopant in a source region and a drain region in the substrate adjacent the gate structure of the transistor in the peripheral masking a number of substrate areas adjacent to the at least partial gate structures of the memory transistors with the first conductive layer during the implant step; and subsequent to the implant step, selectively removing portions of the first conductive layer in the core region to define the respective floating gates.
Claim 8
Independent Claim
169 words
A method for optimizing a voltage junction in a transistor included in a floating gate type memory device, comprising the steps of: forming a gate structure for the transistor on a surface of a substrate in a peripheral region of the substrate; forming at least a partial gate structure for each of a plurality of memory transistors on the surface of the substrate in a core region, the partial gate structure including a first conductive layer configured to function as a floating gate in each of the memory transistors; performing an implant step to implant a dopant in a source region and a drain region in the substrate adjacent the gate structure of the transistor in the peripheral masking a number of substrate areas adjacent to the at least partial gate structures of the memory transistors with the first conductive layer during the implant step; and subsequent to the implant step, selectively removing portions of the first conductive layer in the core region to define the respective floating gates.
Claim 9
Dependent Claim
53 words
The method of claim 6, wherein the peripheral region is to include both a number of high voltage transistors and a number of low voltage transistors, and the implant step is performed at least with respect to a number of source regions and a number of drain regions of the high voltage transistors.
Claim 10
Dependent Claim
52 words
The method of claim 6, further comprising the step of performing a second implant step to implant a dopant at a higher density into the source region and the drain region of the transistor, the second implant step being performed subsequent the step of selectively removing portions of the first conductive layer.
Claim 11
Dependent Claim
33 words
The method of claim 8, wherein the first implant step further comprises the step of implanting the dopant at a lower dose level and a lower energy level than the second implant step.
Claim 12
Dependent Claim
14 words
The method of claim 6, wherein the first conductive layer is made of polysilicon.
Claim 13
Dependent Claim
35 words
The method of claim 6, wherein the gate structure of the transistor in the peripheral region and the at least partial gate structure for each of the memory transistors share a common second conductive layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-12-12 | 2004-06-12 | 2004-12-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-12-12 | 2008-06-12 | 2008-12-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-12-12 | 2012-06-12 | 2012-12-12 | $7700.00 | Window Closed / Lapsed |