US5679585A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for forming metal silicide on a semiconductor surface with minimal effect on pre-existing implants
Assignee: Advanced Micro Devices Inc
•
Filing: 1996-11-15
•
Granted: 1997-10-21
•
Expires: 2016-11-15
Abstract
Abstract An method is provided for fabricating a metal silicide upon a semiconductor topography. The method advantageously performs the anneal cycles at a substantially lower temperature. By employing a high pressure anneal chamber, temperature equilibrium is achieved across the semiconductor topography and especially in small silicide formation areas. The higher pressure helps ensure thermal contact of heated, flowing gas across relatively small geometries in which silicide is to be formed. Substantial metal silicide formation can occur at the higher pressures even under relatively lower temperature conditions. The lower temperature process helps ensure that pre-existing implant regions remain at their initial position. The present metal silicide process and lower temperature anneal is therefore well suited to avoid impurity migration problems such as, for example, threshold skew, parasitic junction capacitance enhancement, and gate oxide degradation.
Inventors
- 👤 Mark I. Gardner
- 👤 Fred N. Hause
- 👤 Derick J. Wristers
- 👤 Dim-Lee Kwong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 07:48
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; Y; Y10; Y10S; Y10S438/00; Y10S438/909
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
174 words
A method for fabricating a metal silicide region upon a semiconductor topography, comprising: providing a semiconductor substrate upon which a semiconductor topography is formed, said topography comprises a substrate dopant region and a polysilicon region configured across a portion of said topography; depositing a metal layer upon said semiconductor topography to form a metal coated topography; placing said metal coated topography into an annealing chamber; annealing said metal coated topography by pressurizing an inert gas within said annealing chamber to a pressure which exceeds 2.0 atmospheres while heating said metal coated topography to a temperature less than 550° C. to form a first metal silicide of first resistivity upon said substrate dopant region and said polysilicon; and further annealing said first metal silicide by pressurizing an inert gas within said annealing chamber to a pressure which exceeds 2.0 atmospheres while heating said first metal silicide to a temperature less than 750° C. to form a second metal silicide of second resistivity less than said first resistivity upon said substrate dopant region and said polysilicon.
Claim 2
Independent Claim
174 words
A method for fabricating a metal silicide region upon a semiconductor topography, comprising: providing a semiconductor substrate upon which a semiconductor topography is formed, said topography comprises a substrate dopant region and a polysilicon region configured across a portion of said topography; depositing a metal layer upon said semiconductor topography to form a metal coated topography; placing said metal coated topography into an annealing chamber; annealing said metal coated topography by pressurizing an inert gas within said annealing chamber to a pressure which exceeds 2.0 atmospheres while heating said metal coated topography to a temperature less than 550° C. to form a first metal silicide of first resistivity upon said substrate dopant region and said polysilicon; and further annealing said first metal silicide by pressurizing an inert gas within said annealing chamber to a pressure which exceeds 2.0 atmospheres while heating said first metal silicide to a temperature less than 750° C. to form a second metal silicide of second resistivity less than said first resistivity upon said substrate dopant region and said polysilicon.
Claim 3
Dependent Claim
14 words
The method as recited in claim 1, wherein said metal layer comprises refractory metal.
Claim 4
Dependent Claim
13 words
The method as recited in claim 1, wherein said metal layer comprises titanium.
Claim 5
Dependent Claim
21 words
The method as recited in claim 1, wherein said dopant region comprises a source or drain region of a MOS transistor.
Claim 6
Dependent Claim
17 words
The method as recited in claim 1, wherein said depositing comprises sputter depositing within a sputter chamber.
Claim 7
Dependent Claim
33 words
The method as recited in claim 5, further comprising: without removing said metal coated topography from said sputter chamber, forming a metal nitride layer upon said metal coated topography prior to said annealing.
Claim 8
Dependent Claim
40 words
The method as recited in claim 6, wherein said without removing comprises retaining said metal coated topography within said sputter chamber and forming said metal nitride layer without intervening exposure of said metal layer to an oxygen-containing or moisture-containing atmosphere.
Claim 9
Dependent Claim
23 words
The method as recited in claim 1, further comprising removing a layer of non-reacted metal from said metal layer subsequent to said annealing.
Claim 10
Dependent Claim
24 words
The method as recited in claim 1, further comprising removing a layer of non-reacted metal from said metal layer prior to said further annealing.
Claim 11
Dependent Claim
13 words
The method as recited in claim 1, wherein said inert gas comprises nitrogen.
Claim 12
Dependent Claim
68 words
The method as recited in claim 10, wherein said annealing comprises moving nitrogen atoms from said inert gas simultaneous with silicon atoms moving from said substrate dopant region and said polysilicon, wherein said nitrogen atoms are moved into said metal layer and bond with metal atoms contained therein, and wherein said bonded nitrogen and metal atoms control distance of movement of said silicon atoms into said metal layer.
Claim 13
Dependent Claim
55 words
The method as recited in claim 11, wherein a majority of said nitrogen atoms are present within a first distance x as measured from the upper surface of said metal layer, and a majority of said silicon atoms are present within a second distance y as measured from the lower surface of said metal layer.
Claim 14
Dependent Claim
15 words
The method as recited in claim 12, wherein distance x is greater than distance y.
Claim 15
Dependent Claim
20 words
The method as recited in claim 1, wherein said pressure exceeds 5.0 atmospheres during said annealing and further annealing steps.
Claim 16
Dependent Claim
20 words
The method as recited in claim 1, wherein said pressure exceeds 10.0 atmospheres during said annealing and further annealing steps.
Claim 17
Dependent Claim
26 words
The method as recited in claim 1, wherein said pressure exceeds 5.0 atmospheres during said annealing step and exceeds 10.0 atmospheres during said further annealing step.
Claim 18
Independent Claim
109 words
A method for forming a conductive contact to an electronic device, comprising: providing a semiconductor topography having an isolated silicon region to be contacted; forming within a sputter chamber a metal layer across said silicon region; loading the metal coated silicon region into an annealing chamber; inserting an ambient gas at a pressure greater than 2.0 atmospheres into said annealing chamber and heating said chamber to a temperature less than 600° C. to react a portion of said metal layer as a first metal silicide of first resistivity upon said silicon region; and removing a non-reacted portion of said metal layer from said metal layer subsequent to said annealing.
Claim 19
Independent Claim
109 words
A method for forming a conductive contact to an electronic device, comprising: providing a semiconductor topography having an isolated silicon region to be contacted; forming within a sputter chamber a metal layer across said silicon region; loading the metal coated silicon region into an annealing chamber; inserting an ambient gas at a pressure greater than 2.0 atmospheres into said annealing chamber and heating said chamber to a temperature less than 600° C. to react a portion of said metal layer as a first metal silicide of first resistivity upon said silicon region; and removing a non-reacted portion of said metal layer from said metal layer subsequent to said annealing.
Claim 20
Dependent Claim
14 words
The method as recited in claim 17, wherein said metal layer comprises refractory metal.
Claim 21
Dependent Claim
17 words
The method as recited in claim 17, wherein said region comprises single crystalline silicon or polycrystalline silicon.
Claim 22
Dependent Claim
33 words
The method as recited in claim 17, further comprising: without removing said metal coated areas from said sputter chamber, forming a metal nitride layer upon said metal coated area prior to said inserting.
Claim 23
Dependent Claim
13 words
The method as recited in claim 17, wherein said ambient gas comprises nitrogen.
Claim 24
Dependent Claim
64 words
The method as recited in claim 21, wherein said inserting comprises moving nitrogen atoms from said ambient gas simultaneous with silicon atoms moving from said silicon region, wherein said nitrogen atoms are moved into said metal layer and bond with metal atoms contained therein, and wherein said bonded nitrogen and metal atoms control distance of movement of said silicon atoms into said metal layer.
Claim 25
Dependent Claim
71 words
The method as recited in claim 17, further comprising: reloading said first metal silicide formed upon said silicon region into said chamber; and reinserting said ambient gas at a pressure greater than 2.0 atmospheres into said chamber and heating said chamber to a temperature less than 750° C. to transform said first metal silicide into a second metal silicide of second resistivity less than said first resistivity upon said silicon area.
Claim 26
Dependent Claim
24 words
The method as recited in claim 17, wherein said first metal silicide comprises TiSi and wherein said second metal silicide comprises TiSi 2 .
References Cited (Backward Citations)
US4293589A
Cited
US4845055A
Cited
US4923822A
Cited
US5043300A
Cited
US5236868A
Cited
US5167716A
Cited
US5242860A
Cited
US5421974A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-10-20 | 2001-04-21 | 2001-10-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-10-20 | 2005-04-21 | 2005-10-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-10-20 | 2009-04-21 | 2009-10-21 | $7700.00 | Window Closed / Lapsed |