US6154711A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Disposition tool for factory process control
Assignee: GlobalFoundries Inc
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Filing: 1997-12-05
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Granted: 2000-11-28
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Expires: 2017-12-05
Abstract
Abstract A method of manufacturing semiconductor wafers using a simulation tool to determine a set of predicted wafer electrical test parameters. The set of predicted wafer electrical test parameters are compared with wafer electrical test specifications tabulated for each process during the manufacturing process. During the comparison, it is determined whether the predicted wafer electrical test parameters are within the specifications for the process and circuit simulations are then conducted using the predicted wafer electrical test parameters. Device performance is predicted from the circuit simulations and the disposition of the wafer lot is determined utilizing tabulated from a disposition performance table.
Inventors
- 👤 Paul J. Steffan
- 👤 Ming Chun Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 11:35
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/70; G03F7/70483; G03F7/70605; G03F7/70616; G03F7/70625; H; H10; H10P; H10P74/00; H10P74/23
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
114 words
A method of manufacturing semiconductor wafers, the method comprising: starting a wafer lot in a process; setting process parameters for the process and running the process; measuring in-line critical dimensions after completion of the process and determining a set of predicted wafer electrical test parameters; comparing the set of predicted wafer electrical test parameters with wafer electrical test specifications tabulated for the process; determining whether the set of predicted wafer electrical test parameters are within the wafer electric test specifications tabulated for the process; performing circuit simulations using the set of predicted wafer electrical test parameters; predicting device performance based on the circuit simulations; and determining a disposition from the predicted device performance data.
Claim 2
Independent Claim
114 words
A method of manufacturing semiconductor wafers, the method comprising: starting a wafer lot in a process; setting process parameters for the process and running the process; measuring in-line critical dimensions after completion of the process and determining a set of predicted wafer electrical test parameters; comparing the set of predicted wafer electrical test parameters with wafer electrical test specifications tabulated for the process; determining whether the set of predicted wafer electrical test parameters are within the wafer electric test specifications tabulated for the process; performing circuit simulations using the set of predicted wafer electrical test parameters; predicting device performance based on the circuit simulations; and determining a disposition from the predicted device performance data.
Claim 3
Dependent Claim
82 words
The method of claim 1 wherein the step of determining a set of predicted wafer electrical test parameters comprises: combining in-line critical dimensions from previous processes run on the wafer lot; with data from previous lots for processes to be run subsequent to the process being run on the wafer lot; and calibration simulation data obtained from a comparison of the set of predicted wafer electrical test parameters and collected actual wafer electrical test measurements taken from previous wafer electrical test measurements.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-28 | 2004-05-29 | 2004-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-28 | 2008-05-29 | 2008-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-28 | 2012-05-29 | 2012-11-28 | $7700.00 | Window Closed / Lapsed |