Patent US6154370A successfully refreshed from Google Patents.
US6154370A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Recessed flip-chip package
Assignee: Bell Semiconductor LLC
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Filing: 1998-07-21
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Granted: 2000-11-28
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Expires: 2018-07-21
Abstract
Abstract The specification describes a recessed chip IC package in which the cavity in the printed wiring board into which the IC chip is recessed is used as a through hole interconnection, thus increasing the interconnection density. If the through cavity interconnections are used as power and ground the signal I/O pads and the signal runners are effectively isolated.
Inventors
- 👤 Yinon Degani
- 👤 Robert Charles Frye
- 👤 Yee Leng Low
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:37
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/63; H10W70/635; H05; H05K; H05K1/00; H05K1/18; H05K1/182; H10W70/65; H10W72/00; H10W72/20; H10W90/00; H10W90/701; H10W90/721; H10W90/722; H10W90/724
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
228 words
An IC package comprising: a. a printed wiring board (PWB) having an upper major surface and a lower major surface, and at least one quadrilateral cavity formed in said upper major surface and extending through said PWB to said lower major surface, b. a first array of interconnection sites on said upper major surface of said PWB along at least one edge of said cavity, c. an intermediate interconnection substrate (IIS) attached to said printed wiring board and substantially covering said cavity, said IIS having an upper major surface and a lower major surface, d. a second array of interconnection sites on the lower major surface of said IIS, with said second array of interconnection sites attached to said first array of interconnection sites on said PWB, e. at least one IC chip attached to said second major surface of said IIS with said at least one IC chip extending into said cavity, f. an interlevel interconnection between a first site on said upper major surface of said PWB and a second site on said lower surface of said PWB, said interconnection comprising a conductive runner extending from said first site along the upper surface of said PWB to the edge of said cavity, along the edge of said cavity, and from the edge of said cavity along the lower surface of said PWB to said second site.
Claim 2
Dependent Claim
228 words
An IC package comprising: a. a printed wiring board (PWB) having an upper major surface and a lower major surface, and at least one quadrilateral cavity formed in said upper major surface and extending through said PWB to said lower major surface, b. a first array of interconnection sites on said upper major surface of said PWB along at least one edge of said cavity, c. an intermediate interconnection substrate (IIS) attached to said printed wiring board and substantially covering said cavity, said IIS having an upper major surface and a lower major surface, d. a second array of interconnection sites on the lower major surface of said IIS, with said second array of interconnection sites attached to said first array of interconnection sites on said PWB, e. at least one IC chip attached to said second major surface of said IIS with said at least one IC chip extending into said cavity, f. an interlevel interconnection between a first site on said upper major surface of said PWB and a second site on said lower surface of said PWB, said interconnection comprising a conductive runner extending from said first site along the upper surface of said PWB to the edge of said cavity, along the edge of said cavity, and from the edge of said cavity along the lower surface of said PWB to said second site.
Claim 3
Dependent Claim
24 words
The IC package of claim 1 wherein the PWB is a multilevel PWB and the said lower major surface corresponds to an interlevel surface.
Claim 4
Dependent Claim
29 words
The IC package of claim 1 in which said interlevel interconnection extends along one edge of said cavity and another interlevel interconnection extends along another edge of said cavity.
Claim 5
Dependent Claim
18 words
The IC package of claim 1 in which the said interlevel interconnection is a power or ground interconnection.
Claim 6
Dependent Claim
12 words
The IC package of claim 1 in which the IIS comprises silicon.
Claim 7
Dependent Claim
17 words
The IC package of claim 1 wherein the interconnections between said arrays of interconnection sites comprise solder.
Claim 8
Dependent Claim
19 words
The IC package of claim 1 further including a ball grid array on the lower surface of said PWB.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-28 | 2004-05-29 | 2004-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-28 | 2008-05-29 | 2008-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-28 | 2012-05-29 | 2012-11-28 | $7700.00 | Window Closed / Lapsed |