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US5869894A Expired / Lapsed US ⏱️ 0.0 years remaining

RF IC package

Assignee: Avago Technologies International Sales Pte Ltd
•
Filing: 1997-07-18
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Granted: 1999-02-09
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Expires: 2017-07-18
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Abstract

Abstract The specification describes a MCM IC package with improved RF grounding. The package has at least one RF IC chip bonded to an interconnect substrate and the substrate is interconnected to an intermediate printed wiring board (IPWB). The IPWB is interconnected in turn to a system printed wiring board (SPWB). The RF IC chip is metallized on the backside, and is flip chip bonded directly to the SPWB thereby eliminating two intermediate interconnections and reducing the impedance of the interconnection between the RF chip and the SWBP.

Inventors

  • 👤 Yinon Degani
  • 👤 Peter R. Smith
  • 👤 King Lien Tai

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 17:56
CPC Classifications
H; H10; H10W; H10W44/00; H10W44/20; H10W70/00; H10W70/60; H10W70/611; H10W90/00; H10W90/401; H10W70/67; H10W70/68; H10W70/681; H10W72/00; H10W72/851; H10W72/874; H10W72/877; H10W90/701; H10W90/721; H10W90/724

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 314 words
An IC MCM package comprising: a. a system printed wiring board (SPWB) having a first surface, an array of SPWB interconnection sites and a common ground plane interconnection site on said surface, b. an intermediate printed wiring board (IPWB) having a picture frame structure with a first array of IPWB interconnection sites on one side of said picture frame structure and a second array of IPWB interconnection sites on the other side of said picture frame structure, said IPWB being interconnected to said SPWB with said first array of IPWB interconnections sites bonded to said array of SPWB interconnection sites, c. a multichip module (MCM) comprising: i. an interconnection substrate with a first array of substrate interconnection sites adapted to be interconnected to an IC chip, ii. a second array of substrate interconnection sites on the interconnection substrate on the same side of the interconnection substrate as the said first array of substrate interconnection sites, said second array of substrate interconnection sites adapted for interconnection with said second array of IPWB interconnection sites, and iii. at least one IC chip having a circuit side and an underside, with an array of chip interconnection sites on said circuit side of said IC chip, said array of chip interconnection sites bonded to said first array of substrate interconnection sites, said IC chip comprising an RF circuit on said circuit side of said chip and a metallization layer on said underside of said chip, said MCM being interconnected to said IPWB with said second array of substrate interconnection sites being bonded to said second array of IPWB interconnection sites, so that the metallization layer on the IC chip is located adjacent the common ground plane interconnection site of the SPWB, the IC MCM package further including means for bonding said metallization layer of said IC chip directly to said common ground plane interconnection site of the SPWB.
Claim 2
Dependent Claim 314 words
An IC MCM package comprising: a. a system printed wiring board (SPWB) having a first surface, an array of SPWB interconnection sites and a common ground plane interconnection site on said surface, b. an intermediate printed wiring board (IPWB) having a picture frame structure with a first array of IPWB interconnection sites on one side of said picture frame structure and a second array of IPWB interconnection sites on the other side of said picture frame structure, said IPWB being interconnected to said SPWB with said first array of IPWB interconnections sites bonded to said array of SPWB interconnection sites, c. a multichip module (MCM) comprising: i. an interconnection substrate with a first array of substrate interconnection sites adapted to be interconnected to an IC chip, ii. a second array of substrate interconnection sites on the interconnection substrate on the same side of the interconnection substrate as the said first array of substrate interconnection sites, said second array of substrate interconnection sites adapted for interconnection with said second array of IPWB interconnection sites, and iii. at least one IC chip having a circuit side and an underside, with an array of chip interconnection sites on said circuit side of said IC chip, said array of chip interconnection sites bonded to said first array of substrate interconnection sites, said IC chip comprising an RF circuit on said circuit side of said chip and a metallization layer on said underside of said chip, said MCM being interconnected to said IPWB with said second array of substrate interconnection sites being bonded to said second array of IPWB interconnection sites, so that the metallization layer on the IC chip is located adjacent the common ground plane interconnection site of the SPWB, the IC MCM package further including means for bonding said metallization layer of said IC chip directly to said common ground plane interconnection site of the SPWB.
Claim 3
Dependent Claim 28 words
The IC MCM package of claim 1 wherein the means for bonding said metallization layer of said IC chip to said common ground plane interconnection site is solder.
Claim 4
Dependent Claim 16 words
The IC MCM package of claim 1 in which the picture frame is filled with epoxy.
Claim 5
Dependent Claim 41 words
The IC MCM package of claim 1 in which the picture frame is filled with anisotropic conductive polymer and the means for bonding said metallization layer of said IC chip to said common ground plane interconnection site is anisotropic conductive polymer.
Claim 6
Dependent Claim 17 words
The IC MCM package of claim 2 in which the said means for bonding comprise conductive epoxy.
Claim 7
Dependent Claim 22 words
The MCM package of claim 1 wherein the said first array of IPWB interconnection sites and said metallization layer are essentially coplanar.
Claim 8
Dependent Claim 24 words
The MCM package of claim 1 in which said second array of substrate interconnection sites is located around the periphery of said interconnection substrate.

References Cited (Backward Citations)

US5198963A Cited
US5608262A Cited
US5646828A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2002-02-08 2002-08-10 2003-02-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2006-02-08 2006-08-10 2007-02-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2010-02-08 2010-08-10 2011-02-09 $7700.00 Window Closed / Lapsed

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