US6153922A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device
Assignee: Renesas Electronics Corp
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Filing: 1998-08-25
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Granted: 2000-11-28
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Expires: 2018-08-25
Abstract
Abstract In a package having an LOC (Lead On Chip) structure in which inner lead portions are partially arranged over a major face of a semiconductor chip, there is a technique for thinning the package and speeding up signal transmission. Specifically, by partially reducing the thicknesses of the signal inner leads arranged over the major face of the semiconductor chip, the thickness of a sealing resin is reduced while ensuring the mechanical strength of the package. Moreover, the signal inner leads arranged over the major face of the semiconductor chip are arranged at predetermined spacings from the major face of the semiconductor chip. The power supplying inner leads are bonded to the major face of the semiconductor chip, thus providing a package having a reduced parasitic capacitance.
Inventors
- 👤 Michiaki Sugiyama
- 👤 Tamaki Wada
- 👤 Masachika Masuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 14:51
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/40; H10W70/411; H10W70/415; H10W72/00; H10W72/50; H10W72/90; H10W72/071; H10W72/075; H10W72/07531; H10W72/07532; H10W72/07533; H10W72/521; H10W72/522; H10W72/531; H10W72/536; H10W72/5363; H10W72/541; H10W72/5449; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/5525; H10W72/553; H10W72/555; H10W72/581; H10W72/59; H10W72/851; H10W72/853; H10W72/865; H10W72/931; H10W72/932; H10W72/934; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W72/952; H10W74/00; H10W90/00; H10W90/701; H10W90/751; H10W90/756
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
214 words
A semiconductor device comprising: a semiconductor chip including a circuit and a plurality of external terminals formed over a major face of a semiconductor substrate, a plurality of leads each including an inner lead portion having a first region, and an inner lead portion having a second region and an outer lead portion formed integrally with said inner lead portions, bonding wires electrically connecting said external terminals and the first regions and the second regions of said inner lead portions, respectively, and a resin member for sealing said semiconductor chip, said inner lead portions and said bonding wires, wherein the first regions and the second regions of said inner lead portions are arranged over the major face of said semiconductor chip, wherein the first regions of said inner lead portions are arranged at predetermined spacings between said major face and said inner leads, wherein the portions of the inner leads arranged over said major face are thinner than the other portions of said inner leads, and wherein the inner leads arranged over said major face are fixed at their leading end portions to the major face of said semiconductor chip through an insulating film, wherein the first regions of said inner lead portions are signal leads whereas said second regions are fixed potential leads.
Claim 2
Dependent Claim
214 words
A semiconductor device comprising: a semiconductor chip including a circuit and a plurality of external terminals formed over a major face of a semiconductor substrate, a plurality of leads each including an inner lead portion having a first region, and an inner lead portion having a second region and an outer lead portion formed integrally with said inner lead portions, bonding wires electrically connecting said external terminals and the first regions and the second regions of said inner lead portions, respectively, and a resin member for sealing said semiconductor chip, said inner lead portions and said bonding wires, wherein the first regions and the second regions of said inner lead portions are arranged over the major face of said semiconductor chip, wherein the first regions of said inner lead portions are arranged at predetermined spacings between said major face and said inner leads, wherein the portions of the inner leads arranged over said major face are thinner than the other portions of said inner leads, and wherein the inner leads arranged over said major face are fixed at their leading end portions to the major face of said semiconductor chip through an insulating film, wherein the first regions of said inner lead portions are signal leads whereas said second regions are fixed potential leads.
Claim 3
Dependent Claim
56 words
A semiconductor device according to claim 1, wherein said semiconductor chip is rectangular, wherein the second regions of said inner lead portions have portions arranged substantially in parallel with the long sides of said semiconductor chip, and wherein said parallel-arranged portions are arranged between said external terminals and the leading end portions of said inner leads.
Claim 4
Dependent Claim
203 words
A semiconductor device comprising: a semiconductor chip including a circuit and a plurality of external terminals formed over the major face of a semiconductor substrate, a plurality of leads each including an inner lead portion having a first region, and an inner lead portion having a second region and an outer lead portion formed integrally with said inner lead portions, bonding wires electrically connecting said external terminals and the first regions and the second regions of said inner lead portions, respectively, and a resin member for sealing said semiconductor chip, said inner lead portions and said bonding wires, wherein the first regions and the second regions of said inner lead portions are arranged over the major face of said semiconductor chip, wherein the first regions of said inner lead portions are arranged at predetermined spacings between said major face and said inner leads, and wherein the portions of the inner leads arranged over said major face are thinner than the other portions of said inner leads but are not fixed at their leading end portions to the major face of said semiconductor chip, wherein the first regions of said inner lead portions are signal leads whereas said second regions are fixed potential leads.
Claim 5
Dependent Claim
203 words
A semiconductor device comprising: a semiconductor chip including a circuit and a plurality of external terminals formed over the major face of a semiconductor substrate, a plurality of leads each including an inner lead portion having a first region, and an inner lead portion having a second region and an outer lead portion formed integrally with said inner lead portions, bonding wires electrically connecting said external terminals and the first regions and the second regions of said inner lead portions, respectively, and a resin member for sealing said semiconductor chip, said inner lead portions and said bonding wires, wherein the first regions and the second regions of said inner lead portions are arranged over the major face of said semiconductor chip, wherein the first regions of said inner lead portions are arranged at predetermined spacings between said major face and said inner leads, and wherein the portions of the inner leads arranged over said major face are thinner than the other portions of said inner leads but are not fixed at their leading end portions to the major face of said semiconductor chip, wherein the first regions of said inner lead portions are signal leads whereas said second regions are fixed potential leads.
Claim 6
Dependent Claim
321 words
A semiconductor device comprising: a semiconductor chip including an integrated circuit and a plurality of external terminals formed over a major face of said semiconductor chip, a plurality of leads each including an inner lead portion and an outer lead portion formed integrally with said inner lead portion, portions of said inner lead portions being arranged over the major face of said semiconductor chip and being electrically connected to the corresponding external terminals, and a resin member for sealing the inner lead portions of said plurality of leads and said semiconductor chip, wherein said inner lead portions each include a first surface on the major face side of said semiconductor chip, a second surface on the opposite side to said first surface, a first portion positioned over the major face of said semiconductor chip and a second portion formed integrally with said first portion and positioned outside the major face of said semiconductor chip, wherein the first portions of said inner lead portions are made thinner than said second portions in the thickness direction of said semiconductor chip, wherein the first surfaces of the first portions of said inner lead portions are spaced farther from said semiconductor chip in the thickness direction of said semiconductor chip than the first surfaces of the second portions of said inner lead portions, wherein said inner lead portions and the corresponding external terminals are connected through wires; wherein said plurality of leads include signal leads and fixed potential leads, wherein the inner lead portions of said fixed potential leads are partially arranged over the major face of said semiconductor chip between said plurality of external terminals of the leading ends of the inner lead portions of said signal leads, and wherein the wires connecting the inner lead portions of said signal leads and the corresponding external terminals are so arranged as to cross over portions of the inner lead portions of said fixed potential leads.
Claim 7
Dependent Claim
321 words
A semiconductor device comprising: a semiconductor chip including an integrated circuit and a plurality of external terminals formed over a major face of said semiconductor chip, a plurality of leads each including an inner lead portion and an outer lead portion formed integrally with said inner lead portion, portions of said inner lead portions being arranged over the major face of said semiconductor chip and being electrically connected to the corresponding external terminals, and a resin member for sealing the inner lead portions of said plurality of leads and said semiconductor chip, wherein said inner lead portions each include a first surface on the major face side of said semiconductor chip, a second surface on the opposite side to said first surface, a first portion positioned over the major face of said semiconductor chip and a second portion formed integrally with said first portion and positioned outside the major face of said semiconductor chip, wherein the first portions of said inner lead portions are made thinner than said second portions in the thickness direction of said semiconductor chip, wherein the first surfaces of the first portions of said inner lead portions are spaced farther from said semiconductor chip in the thickness direction of said semiconductor chip than the first surfaces of the second portions of said inner lead portions, wherein said inner lead portions and the corresponding external terminals are connected through wires; wherein said plurality of leads include signal leads and fixed potential leads, wherein the inner lead portions of said fixed potential leads are partially arranged over the major face of said semiconductor chip between said plurality of external terminals of the leading ends of the inner lead portions of said signal leads, and wherein the wires connecting the inner lead portions of said signal leads and the corresponding external terminals are so arranged as to cross over portions of the inner lead portions of said fixed potential leads.
Claim 8
Dependent Claim
30 words
A semiconductor device according to claim 4, wherein the first portions of said inner lead portions are bonded to the major face of said semiconductor chip through an insulating film.
Claim 9
Dependent Claim
28 words
A semiconductor device according to claim 4, wherein the first portions of said inner lead portions are bonded to the major face of said semiconductor chip through adhesive.
Claim 10
Dependent Claim
363 words
A semiconductor device comprising: a semiconductor chip including an integrated circuit and a plurality of external terminals formed over a major face of the semiconductor chip, a plurality of signal leads each including an inner lead portion and an outer lead portion formed integrally with said inner lead portions, portions of said inner lead portions being arranged over the major face of said semiconductor chip and electrically connected to the corresponding external terminals through wires, fixed potential leads each including an inner lead portion and an outer lead portion formed integrally with said inner lead portions, said inner lead portions being partially arranged over the major face of said semiconductor chip and electrically connected to the corresponding external terminals, and a resin member for sealing the inner lead portions of said plurality of signal leads, the inner lead portions of said fixed potential leads, and said semiconductor chip, wherein said inner lead portions of said signal leads each include a first surface on the major face side of said semiconductor chip, a second surface on the opposite side to said first surface, a first portion positioned over the major face of said semiconductor chip, and a second portion formed integrally with said first portions and positioned outside the major face of said semiconductor chip, wherein the first portions of said inner lead portions of said signal leads are made thinner than said second portions in the thickness direction of said semiconductor chip, wherein the first surfaces of the first portions of said inner lead portions of said signal leads are more spaced from said semiconductor chip in the thickness direction of said semiconductor chip than the first surfaces of the second portions of said inner lead portions, wherein the inner lead portions of said fixed potential leads are partially arranged over the major face of said semiconductor chip between the leading ends of the inner lead portions of said signal leads and said plurality of external terminals, and wherein the inner lead portions of said fixed potential leads are partially arranged lower in the thickness direction of said semiconductor chip than the leading ends of the inner lead portions of said signal leads.
Claim 11
Dependent Claim
363 words
A semiconductor device comprising: a semiconductor chip including an integrated circuit and a plurality of external terminals formed over a major face of the semiconductor chip, a plurality of signal leads each including an inner lead portion and an outer lead portion formed integrally with said inner lead portions, portions of said inner lead portions being arranged over the major face of said semiconductor chip and electrically connected to the corresponding external terminals through wires, fixed potential leads each including an inner lead portion and an outer lead portion formed integrally with said inner lead portions, said inner lead portions being partially arranged over the major face of said semiconductor chip and electrically connected to the corresponding external terminals, and a resin member for sealing the inner lead portions of said plurality of signal leads, the inner lead portions of said fixed potential leads, and said semiconductor chip, wherein said inner lead portions of said signal leads each include a first surface on the major face side of said semiconductor chip, a second surface on the opposite side to said first surface, a first portion positioned over the major face of said semiconductor chip, and a second portion formed integrally with said first portions and positioned outside the major face of said semiconductor chip, wherein the first portions of said inner lead portions of said signal leads are made thinner than said second portions in the thickness direction of said semiconductor chip, wherein the first surfaces of the first portions of said inner lead portions of said signal leads are more spaced from said semiconductor chip in the thickness direction of said semiconductor chip than the first surfaces of the second portions of said inner lead portions, wherein the inner lead portions of said fixed potential leads are partially arranged over the major face of said semiconductor chip between the leading ends of the inner lead portions of said signal leads and said plurality of external terminals, and wherein the inner lead portions of said fixed potential leads are partially arranged lower in the thickness direction of said semiconductor chip than the leading ends of the inner lead portions of said signal leads.
Claim 12
Dependent Claim
53 words
A semiconductor device according to claim 7, wherein the inner lead portions of said fixed potential leads are partially bonded to the major face of said semiconductor chip with adhesive, wherein the inner lead portions of said signal leads are spaced at their leading ends from the major face of said semiconductor chip.
Claim 13
Dependent Claim
33 words
A semiconductor device according to claim 7, wherein the inner lead portions of said signal leads bonded at their leading ends to the major face of said semiconductor chip through an insulating film.
Claim 14
Dependent Claim
43 words
A semiconductor device according to claim 7, wherein the wires for connecting the inner lead portions of said signal leads and the corresponding external terminals are so arranged as to cross over portions of the inner lead portions of said fixed potential leads.
Claim 15
Dependent Claim
446 words
A semiconductor device comprising: a semiconductor chip including an integrated circuit and a plurality of external terminals formed over a major face of the semiconductor chip, a plurality of signal leads each including an inner lead portion and an outer lead portion formed integrally with said inner lead portion, portions of said inner lead portions being arranged over the major face of said semiconductor chip and electrically connected to the corresponding external terminals through wires, fixed potential leads each including an inner lead portion and an outer lead portion formed integrally with said inner lead portions, said inner lead portions being partially arranged over the major face of said semiconductor chip and electrically connected to the corresponding external terminals, and a resin member for sealing the inner lead portions of said plurality of signal leads, the inner lead portions of said fixed potential leads, and said semiconductor chip, wherein said inner lead portions of said signal leads each includes a first surface on the major face side of said semiconductor chip, a second surface on the opposite side to said first surface, a first portion positioned over the major face of said semiconductor chip, and a second portion formed integrally with said first portion and positioned outside the major face of said semiconductor chip, wherein the first portions of said inner lead portions of said signal leads are made thinner than said second portions in the thickness direction of said semiconductor chip, wherein the first portions of said inner lead portions of said signal leads have leading end portions to be connected to said wires, wherein the first surfaces of the first portions of said inner lead portions of said signal leads other than said leading end portions are more spaced from said semiconductor chip in the thickness direction of said semiconductor chip than the first surfaces of the second portions of said inner lead portions, wherein the first portions of said inner lead portions of said signal leads are arranged lower in the thickness direction of said semiconductor chip than the first portions of said inner lead portions of said signal leads other than said leading end portions, wherein the inner lead portions of said fixed potential leads are partially arranged over the major face of said semiconductor chip between the leading end portions of the first portions of the inner lead portions of said signal leads and said plurality of external terminals, and wherein the inner lead portions of said fixed potential leads are partially arranged lower in the thickness direction of said semiconductor chip than the first portions of the inner lead portions of said signal leads other than said leading end portions.
Claim 16
Dependent Claim
446 words
A semiconductor device comprising: a semiconductor chip including an integrated circuit and a plurality of external terminals formed over a major face of the semiconductor chip, a plurality of signal leads each including an inner lead portion and an outer lead portion formed integrally with said inner lead portion, portions of said inner lead portions being arranged over the major face of said semiconductor chip and electrically connected to the corresponding external terminals through wires, fixed potential leads each including an inner lead portion and an outer lead portion formed integrally with said inner lead portions, said inner lead portions being partially arranged over the major face of said semiconductor chip and electrically connected to the corresponding external terminals, and a resin member for sealing the inner lead portions of said plurality of signal leads, the inner lead portions of said fixed potential leads, and said semiconductor chip, wherein said inner lead portions of said signal leads each includes a first surface on the major face side of said semiconductor chip, a second surface on the opposite side to said first surface, a first portion positioned over the major face of said semiconductor chip, and a second portion formed integrally with said first portion and positioned outside the major face of said semiconductor chip, wherein the first portions of said inner lead portions of said signal leads are made thinner than said second portions in the thickness direction of said semiconductor chip, wherein the first portions of said inner lead portions of said signal leads have leading end portions to be connected to said wires, wherein the first surfaces of the first portions of said inner lead portions of said signal leads other than said leading end portions are more spaced from said semiconductor chip in the thickness direction of said semiconductor chip than the first surfaces of the second portions of said inner lead portions, wherein the first portions of said inner lead portions of said signal leads are arranged lower in the thickness direction of said semiconductor chip than the first portions of said inner lead portions of said signal leads other than said leading end portions, wherein the inner lead portions of said fixed potential leads are partially arranged over the major face of said semiconductor chip between the leading end portions of the first portions of the inner lead portions of said signal leads and said plurality of external terminals, and wherein the inner lead portions of said fixed potential leads are partially arranged lower in the thickness direction of said semiconductor chip than the first portions of the inner lead portions of said signal leads other than said leading end portions.
Claim 17
Dependent Claim
45 words
A semiconductor device according to claim 11, wherein portions of the inner lead portions of said fixed potential leads and the leading end portions of the inner lead portions of said signal leads are bonded to the major face of said semiconductor chip with adhesive.
Claim 18
Dependent Claim
42 words
A semiconductor device according to claim 11, wherein the wires connecting the inner lead portions of said signal leads and the corresponding external terminals are so arranged as to cross over portions of the inner lead portions of said fixed potential leads.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-28 | 2004-05-29 | 2004-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-28 | 2008-05-29 | 2008-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-28 | 2012-05-29 | 2012-11-28 | $7700.00 | Window Closed / Lapsed |