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Patent US6153448A successfully refreshed from Google Patents.
US6153448A
Expired / Lapsed
US
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Semiconductor device manufacturing method
Assignee: Kioxia Corp
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Filing: 1999-08-20
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Granted: 2000-11-28
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Expires: 2019-08-20
Abstract
Abstract There is provided a semiconductor device having a chip-size package structure comprising a semiconductor pellet including semiconductor elements, wires, a plurality of electrode pads, and final protection film, an insulation layer serving also as a sealing layer formed to cover the entire surface of the semiconductor pellet having a via hole portion above each of the electrode pads in association therewith, a plurality of wiring patterns formed with a via hole wiring portion electrically connected to the electrode pad at the bottom of each of the via hole portions of the insulation layer and formed with a land portion connected thereto and located in a position offset from the via hole portion, and an external electrode in the form of a ball provided on the land portion of each of the wiring patterns. This makes it possible to provide a semiconductor device in a chip-size package structure in which the length of wires led out from electrode pads is shortened as much as possible to lead out wires from electrode pads near the center of the pellet easily and to allow a pellet having an increased number of external electrodes to be accommodated.
Inventors
- 👤 Takuya Takahashi
- 👤 Akio Katsumata
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 22:28
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/10; H10W74/111; H10W74/129; H10D; H10D62/00; H10D62/10; H10D62/117; H10W70/00; H10W70/01; H10W70/05; H10W72/00; H10W72/01; H10W72/012; H10W72/01221; H10W72/01225; H10W72/019; H10W72/0198; H10W72/20; H10W72/241; H10W72/242; H10W72/244; H10W72/251; H10W72/252; H10W72/29; H10W72/50; H10W72/851; H10W72/853; H10W72/859; H10W72/90; H10W72/921; H10W72/922; H10W72/923; H10W72/941; H10W72/944; H10W72/9445; H10W72/951; H10W72/952; H10W90/00; H10W90/701; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
208 words
A method for manufacturing a semiconductor device comprising the steps of: forming a plurality of chip regions including a plurality of electrode pads on a semiconductor wafer; forming a barrier metal layer on said semiconductor wafer and performing etching to selectively leave the barrier metal on the electrode pad in each of said chip region and in a predetermined region surrounding the same; forming line grooves to a depth which is halfway the thickness of the substrate between the chip regions of said semiconductor wafer; forming an insulation layer serving also as a sealing layer having openings for via holes in correspondence to the arrangement of said barrier metal; forming wiring patterns including via hole wiring portions connected to said barrier metal at the bottom of said openings for via holes and including land portions connected thereto and arranged regularly in the form of a matrix in positions on the tape insulation layer offset from said via hole portions; mounting external electrodes in the form of balls on the land portions of said wiring patterns; and cutting the wafer with a dicing saw along the center lines of said line grooves to divide it into semiconductor devices in a chip-size package structure including a ball grid array electrode.
Claim 2
Independent Claim
208 words
A method for manufacturing a semiconductor device comprising the steps of: forming a plurality of chip regions including a plurality of electrode pads on a semiconductor wafer; forming a barrier metal layer on said semiconductor wafer and performing etching to selectively leave the barrier metal on the electrode pad in each of said chip region and in a predetermined region surrounding the same; forming line grooves to a depth which is halfway the thickness of the substrate between the chip regions of said semiconductor wafer; forming an insulation layer serving also as a sealing layer having openings for via holes in correspondence to the arrangement of said barrier metal; forming wiring patterns including via hole wiring portions connected to said barrier metal at the bottom of said openings for via holes and including land portions connected thereto and arranged regularly in the form of a matrix in positions on the tape insulation layer offset from said via hole portions; mounting external electrodes in the form of balls on the land portions of said wiring patterns; and cutting the wafer with a dicing saw along the center lines of said line grooves to divide it into semiconductor devices in a chip-size package structure including a ball grid array electrode.
Claim 3
Dependent Claim
53 words
A method for manufacturing a semiconductor device according to claim 1, wherein at said step of forming the insulation layer serving also as a sealing layer, a thermally hardened epoxy tape formed with said openings for via holes using a punching process is applied to said semiconductor wafer using a thermo-compression bonding process.
Claim 4
Dependent Claim
24 words
A method for manufacturing a semiconductor device according to claim 2, wherein a metal core material is added to said thermally hardened epoxy tape.
Claim 5
Dependent Claim
55 words
A method for manufacturing a semiconductor device according to claim 1, wherein at said step of forming the insulation layer serving also as a sealing layer, said semiconductor wafer is coated with a liquid material such as photosensitive epoxy and, thereafter, patterning is performed using a photolithographic process to form said openings for via holes.
Claim 6
Dependent Claim
70 words
A method for manufacturing a semiconductor device according to claim 1, wherein at said step of the wiring patterns, an electroless plating process is performed to plate the entire surface of said semiconductor wafer with Cu and etching is performed using a photolithographic process to leave predetermined Cu patterns and, thereafter, an electrolytic process is performed to form a metal layer made of Au and Ni on the Cu patterns.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-28 | 2004-05-29 | 2004-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-28 | 2008-05-29 | 2008-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-28 | 2012-05-29 | 2012-11-28 | $7700.00 | Window Closed / Lapsed |