User-controlled delay circuit for a programmable logic device

Claim 2

An input block for an integrated circuit (IC), the input block comprising: a) an input terminal adapted to receive an input signal from a first source, the input signal including a first signal transition; b) a control terminal adapted to receive a delay instruction from a variable signal source, the delay instruction providing indicia of a delay period to apply to the first input signal, the variable signal source progressively changing the delay instruction such that the delay period progressively changes; c) a variable delay circuit having: an input node connected to the input terminal; an output node; at least one delay element for providing a delayed version of the input signal on the output node; and a control node adapted to receive the delay instruction from the control terminal, wherein the delayed version of the input signal includes a second signal transition delayed from the first signal transition by the delay period specified by the delay instruction; and d) a monitor element whereby the delayed version of the input signal on the output node is monitored for a metastable condition.

Claim 3

The input block of claim 1, wherein the IC is a programmable logic device.

Claim 4

The input block of claim 1, wherein the variable delay circuit includes a plurality of delay elements and a multiplexer adapted to selectively connect the input node to the output node through different numbers of the delay elements.

Claim 5

The input block of claim 3, wherein the control node is connected to a select terminal of the multiplexer.

Claim 6

The input block of claim 1, further comprising a phase comparator having a first input terminal connected to the output node of the variable delay circuit, a second input terminal providing a reference clock signal, and an output terminal.

Claim 7

An input block for an integrated circuit (IC), the input block comprising: a) an input terminal adapted to receive an input signal from a first source, the input signal including a first signal transition; b) a control terminal adapted to receive a delay instruction from a variable signal source, the delay instruction providing indicia of a delay period to apply to the first input signal; and c) a variable delay circuit having: an input node connected to the input terminal; an output node; at least one delay element for providing a delayed version of the input signal on the output node, wherein the delayed version of the input signal includes a second signal transition delayed from the first signal transition by the delay period specified by the delay instruction; and a control node adapted to receive the delay instruction from the control terminal, wherein the variable signal source comprises a feedback circuit having at least one input terminal connected to the output node of the variable delay circuit and at least one output terminal providing control information to the control node of the variable delay circuit.

Claim 8

An input block for an integrated circuit (IC), the input block comprising: a) an input terminal adapted to receive an input signal from a first source, the input signal including a first signal transition; b) a control terminal adapted to receive a delay instruction from a variable signal source, the delay instruction providing indicia of a delay period to apply to the first input signal; and c) a variable delay circuit having: an input node connected to the input terminal; an output node; at least one delay element for providing a delayed version of the input signal on the output node, wherein the delayed version of the input signal includes a second signal transition delayed from the first signal transition by the delay period specified by the delay instruction; and a control node adapted to receive the delay instruction from the control terminal, wherein the variable signal source comprises a feedback circuit having at least one input terminal connected to the output node of the variable delay circuit and at least one output terminal providing control information to the control node of the variable delay circuit.

Claim 9

The input block of claim 6, wherein the feedback circuit enables automatic adjustment of a setup time for the input block.

Claim 10

An input block for an integrated circuit (IC), the input block comprising: a) an input terminal adapted to receive an input signal from a first source, the input signal including a first signal transition; b) a control terminal adapted to receive a delay instruction from a variable signal source, the delay instruction providing indicia of a delay period to apply to the first input signal; c) a variable delay circuit having: an input node connected to the input terminal; an output node; at least one delay element for providing a delayed version of the input signal on the output node, wherein the delayed version of the input signal includes a second signal transition delayed from the first signal transition by the delay period specified by the delay instruction; and a control node adapted to receive the delay instruction from the control terminal; and d) a phase comparator having a first input terminal connected to the output node of the variable delay circuit, a second input terminal providing a reference clock signal, and an output terminal, wherein the variable signal source comprises a feedback circuit having an input terminal connected to the output terminal of the phase comparator and at least one output terminal providing control information to the control node of the variable delay circuit.

Claim 11

An input block for an integrated circuit (IC), the input block comprising: a) an input terminal adapted to receive an input signal from a first source, the input signal including a first signal transition; b) a control terminal adapted to receive a delay instruction from a variable signal source, the delay instruction providing indicia of a delay period to apply to the first input signal; c) a variable delay circuit having: an input node connected to the input terminal; an output node; at least one delay element for providing a delayed version of the input signal on the output node, wherein the delayed version of the input signal includes a second signal transition delayed from the first signal transition by the delay period specified by the delay instruction; and a control node adapted to receive the delay instruction from the control terminal; and d) a phase comparator having a first input terminal connected to the output node of the variable delay circuit, a second input terminal providing a reference clock signal, and an output terminal, wherein the variable signal source comprises a feedback circuit having an input terminal connected to the output terminal of the phase comparator and at least one output terminal providing control information to the control node of the variable delay circuit.

Claim 12

The input block of claim 8, wherein the feedback circuit enables automatic adjustment of the setup time for the input block.

Claim 13

An integrated circuit, comprising: a first variable-delay circuit adapted to receive an input signal on an input terminal and to output a delayed version of the input signal on a first output terminal, the first variable delay circuit including at least one control terminal adapted to receive controls signals indicative of a delay duration to apply to the input signal; a control-signal generator having at least one output terminal connected to the at least one control terminal of the first variable-delay circuit, the control-signal generator being adapted to provide the control signals indicative of the delay duration, the control-signal generator progressively changing the control signals such that the delay duration progressively changes; and means for monitoring the delayed version of the input signal for a metastable condition.

Claim 14

An integrated circuit, comprising: a first variable-delay circuit adapted to receive an input signal on an input terminal and to output a delayed version of the input signal on a first output terminal, the first variable delay circuit including at least one control terminal adapted to receive controls signals indicative of a delay duration to apply to the input signal; a control-signal generator having at least one output terminal connected to the at least one control terminal of the first variable-delay circuit, the control-signal generator being adapted to provide the control signals indicative of the delay duration, the control-signal generator progressively changing the control signals such that the delay duration progressively changes; and means for monitoring the delayed version of the input signal for a metastable condition.

Claim 15

The integrated circuit of claim 10, wherein the integrated circuit is a programmable logic device.

Claim 16

The integrated circuit of claim 11, wherein the first variable-delay circuit is a portion of an input block of the programmable logic device.

Claim 17

The integrated circuit of claim 10, wherein the control-signal generator comprises a control input terminal, and the integrated circuit further comprises a phase comparator having an input terminal connected to the first output terminal of the first variable delay circuit and an output terminal connected to the control input terminal of the control-signal generator.

Claim 18

The integrated circuit of claim 10, wherein the control-signal generator is an up/down counter.

Claim 19

The integrated circuit of claim 10, further comprising a second variable-delay circuit having at least one control terminal connected to the at least one output terminal of the control-signal generator.