US5790611A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for adjusting the phase of a digital signal
Assignee: Avago Technologies International Sales Pte Ltd
•
Filing: 1994-08-12
•
Granted: 1998-08-04
•
Expires: 2014-08-12
Abstract
Abstract A method and apparatus for improving the phase granularity when changing the phase of a digital signal. The present invention doubles the phase shift granularity of a phase shifting system by either adding or not adding one-half unit of phase delay to the digital signal being phase shifted. When increasing phase delay is being added to the digital signal, no additional phase delay is added to the digital signal. When decreasing phase delay is being adding to the digital signal, one-half unit of phase delay is added to the digital signal. Thus, whenever a change is made between increasing or decreasing phase delay, a one-half unit phase delay is introduced which effectively doubles the phase delay granularity of the phase delay system at the point of phase delay reversal.
Inventors
- 👤 Jen-Hsun Huang
- 👤 Stony Peng
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 00:59
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; G; G06; G06F; G06F1/00; G06F1/04; G06F1/10; H03; H03K; H03K5/00; H03K5/13; H03K5/131; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
149 words
A method for adjusting the phase of a digital signal, comprising the steps of: delaying a digital signal in time by a plurality of selectable time delay intervals, each interval having a predefined time; determining the phase difference between the digital signal and a reference clock; increasing the amount of time delay of the digital signal when the digital signal is leading in phase with respect to said reference clock; decreasing the amount of time delay of the digital signal when the digital signal is lagging in phase with respect to said reference clock; adding a time delay interval of approximately one-half of the predefined time to the digital signal when changing from increasing time delay to decreasing time delay of the digital signal; and adding substantially no additional time delay to the digital signal when changing from decreasing time delay to increasing time delay of the digital signal.
Claim 2
Independent Claim
149 words
A method for adjusting the phase of a digital signal, comprising the steps of: delaying a digital signal in time by a plurality of selectable time delay intervals, each interval having a predefined time; determining the phase difference between the digital signal and a reference clock; increasing the amount of time delay of the digital signal when the digital signal is leading in phase with respect to said reference clock; decreasing the amount of time delay of the digital signal when the digital signal is lagging in phase with respect to said reference clock; adding a time delay interval of approximately one-half of the predefined time to the digital signal when changing from increasing time delay to decreasing time delay of the digital signal; and adding substantially no additional time delay to the digital signal when changing from decreasing time delay to increasing time delay of the digital signal.
Claim 3
Dependent Claim
45 words
The method of claim 1, wherein the step of delaying the digital signal comprises the step of delaying the digital signal in a digital delay line having a plurality of selectable delay taps, each tap having a time delay interval of approximately said predefined time.
Claim 4
Dependent Claim
33 words
The method of claim 2, wherein the step of increasing the amount of time delay of the digital signal comprises the step of selecting respectively increasing delay taps of the digital delay line.
Claim 5
Dependent Claim
33 words
The method of claim 2, wherein the step of decreasing the amount of time delay of the digital signal comprises the step of selecting respectively decreasing delay taps of the digital delay line.
Claim 6
Dependent Claim
50 words
The method of claim 2, after the step of determining the phase difference between the digital signal and the reference clock, further comprising the step of selecting respective delay taps of the digital delay line such that the phase difference between the digital signal and the reference clock is minimized.
Claim 7
Independent Claim
158 words
A system for adjusting the phase of a digital signal comprising: means for delaying a digital signal in time by a plurality of selectable time delay intervals, each interval having a predefined time; means for determining the phase difference between the digital signal and a reference clock; means for increasing the amount of time delay of the digital signal when the digital signal is leading in phase with respect to said reference clock; means for decreasing the amount of time delay of the digital signal when the digital signal is lagging in phase with respect to said reference clock; means for adding a time delay interval of approximately one-half of the predefined time to the digital signal when changing from increasing time delay to decreasing time delay of the digital signal; and means for adding substantially no additional time delay to the digital signal when changing from decreasing time delay to increasing time delay of the digital signal.
Claim 8
Independent Claim
158 words
A system for adjusting the phase of a digital signal comprising: means for delaying a digital signal in time by a plurality of selectable time delay intervals, each interval having a predefined time; means for determining the phase difference between the digital signal and a reference clock; means for increasing the amount of time delay of the digital signal when the digital signal is leading in phase with respect to said reference clock; means for decreasing the amount of time delay of the digital signal when the digital signal is lagging in phase with respect to said reference clock; means for adding a time delay interval of approximately one-half of the predefined time to the digital signal when changing from increasing time delay to decreasing time delay of the digital signal; and means for adding substantially no additional time delay to the digital signal when changing from decreasing time delay to increasing time delay of the digital signal.
Claim 9
Dependent Claim
37 words
The system of claim 6, wherein the means for delaying the digital signal is a digital delay line having a plurality of selectable delay taps, each tap having a time delay interval of approximately said predefined time.
Claim 10
Dependent Claim
32 words
The system of claim 7, wherein the means for increasing the amount of time delay of the digital signal comprises logic for selecting respectively increasing delay taps of said digital delay line.
Claim 11
Dependent Claim
32 words
The system of claim 7, wherein the means for decreasing the amount of time delay of the digital signal comprises logic for selecting respectively decreasing delay taps of said digital delay line.
Claim 12
Dependent Claim
18 words
The system of claim 6, wherein the means for determining the phase difference is a digital phase detector.
Claim 13
Dependent Claim
41 words
The system of claim 6, further comprising a selector circuit for selecting between the means for adding the time delay interval of approximately one-half of the predefined time or means for adding substantially no additional time delay to the digital signal.
Claim 14
Independent Claim
289 words
An apparatus for adjusting the phase of a digital signal, comprising: a digital delay line having a plurality of selectable delay taps with predefined time delay intervals, said digital delay line adapted to receive the digital signal and output a delayed version of the digital signal; a digital phase detector having reference and signal inputs and an output, said digital phase detector output indicating relative phase difference between the reference and signal inputs; a reference clock, said reference clock connected to the reference input of said digital phase detector; a half delay circuit for delaying the digital signal approximately half the delay time of the predetermined time delay interval of said digital delay line; said half delay circuit having a control input used to select whether the digital signal is delayed by half a time interval or substantially no delay; said half delay circuit connected between the output of said digital delay line and the signal input of said digital phase detector; and a logic control circuit having a control input connected to the output of said digital phase detector, a first output connected to said digital delay line for controlling selection of a delay tap, and a second output connected to the control input of said half delay circuit for controlling whether the digital signal is delayed by half a time interval or substantially no delay; wherein said logic control circuit instructs said half delay circuit to add approximately half the delay time to the digital signal when selecting decreasing time delay taps of said digital delay line, and said logic control circuit instructs said half delay circuit to add substantially no delay to the digital signal when selecting increasing time delay taps of said digital delay line.
Claim 15
Independent Claim
289 words
An apparatus for adjusting the phase of a digital signal, comprising: a digital delay line having a plurality of selectable delay taps with predefined time delay intervals, said digital delay line adapted to receive the digital signal and output a delayed version of the digital signal; a digital phase detector having reference and signal inputs and an output, said digital phase detector output indicating relative phase difference between the reference and signal inputs; a reference clock, said reference clock connected to the reference input of said digital phase detector; a half delay circuit for delaying the digital signal approximately half the delay time of the predetermined time delay interval of said digital delay line; said half delay circuit having a control input used to select whether the digital signal is delayed by half a time interval or substantially no delay; said half delay circuit connected between the output of said digital delay line and the signal input of said digital phase detector; and a logic control circuit having a control input connected to the output of said digital phase detector, a first output connected to said digital delay line for controlling selection of a delay tap, and a second output connected to the control input of said half delay circuit for controlling whether the digital signal is delayed by half a time interval or substantially no delay; wherein said logic control circuit instructs said half delay circuit to add approximately half the delay time to the digital signal when selecting decreasing time delay taps of said digital delay line, and said logic control circuit instructs said half delay circuit to add substantially no delay to the digital signal when selecting increasing time delay taps of said digital delay line.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-03 | 2002-02-02 | 2002-08-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-03 | 2006-02-02 | 2006-08-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-03 | 2010-02-02 | 2010-08-04 | $7700.00 | Window Closed / Lapsed |