Arrangement of data input/output circuits for use in a semiconductor memory device

Claim 2

A semiconductor memory device formed on a chip, comprising: a plurality of memory cell blocks arranged in rows and columns, wherein each memory cell block comprises a plurality of memory cells for storing data; a plurality of data input/output circuits divided into a first group and a second group, wherein the first group and the second group are associated with and disposed between a respective subset of the memory cell blocks, and the data input/output circuits have a plurality of data input/output pins; and a plurality of address signal circuits arranged between the first group and the second group, for receiving externally applied address signals, wherein the semiconductor memory device is packed using a Non-Outer-DQ-Inner-Control (NON-ODIC) type package having a structure such that the data input/output pins of the data input/output circuits of the first and second groups are collectively arranged adjacent to each other.

Claim 3

The semiconductor memory device according to claim 1, wherein the data input/output circuits comprise a data input/output pad and a data input/output buffer.

Claim 4

The semiconductor memory device according to claim 1, wherein the package comprises a NON-ODIC type ball grip array package.

Claim 5

The semiconductor memory device according to claim 1, wherein the address signal circuits comprise an address signal pad and an address signal buffer.

Claim 6

The semiconductor memory device according to claim 1, further comprising a plurality of control signal circuits arranged adjacent to the data input/output circuits of the first group and between the subset of memory cell blocks corresponding to the first group.

Claim 7

The semiconductor memory device according to claim 5, wherein the control signal circuits comprise a control signal pad and a control signal buffer.

Claim 8

The semiconductor memory device according to claim 5, wherein the data input/output circuits comprise a data input/output pad and a data input/output buffer, the address signal circuits comprise an address signal pad and an address signal buffer, the control signal circuits comprise a control signal pad and a control signal buffer, and the semiconductor memory device further comprises a plurality of wires for electrically connecting the data input/output, address signal, and control signal pads to corresponding pins of the package, the wires being arranged in a multi layer structure.

Claim 9

A semiconductor memory device formed on a chip comprising: a plurality of memory cell blocks arranged in rows and columns, wherein each memory cell block comprises a plurality of memory cells for storing data; a plurality of data input/output circuits divided into a first group and a second group, wherein the first group and the second group are associated with and disposed between a respective subset of the memory cell blocks, and the data input/output circuits have a data input/output pad, a data input/output buffer, and a plurality of data input/output pins; a plurality of address signal circuits arranged between the first group and the second group, for receiving externally applied address signals, wherein the address signal circuits have an address signal pad and an address signal buffer; and a plurality of control signal circuits arranged adjacent to the data input/output circuits of the first group and between the subset of memory cell blocks corresponding to the first group of data input/output circuits, wherein the control signal circuits have a control signal pad and a control signal buffer, and the semiconductor memory device is packed using a Non-Outer-DQ-Inner-Control (NON-ODIC) type package having a structure such that the data input/output pins of the data input/output circuits of the first group and the second group are collectively arranged adjacent to each other.

Claim 10

A semiconductor memory device formed on a chip comprising: a plurality of memory cell blocks arranged in rows and columns, wherein each memory cell block comprises a plurality of memory cells for storing data; a plurality of data input/output circuits divided into a first group and a second group, wherein the first group and the second group are associated with and disposed between a respective subset of the memory cell blocks, and the data input/output circuits have a data input/output pad, a data input/output buffer, and a plurality of data input/output pins; a plurality of address signal circuits arranged between the first group and the second group, for receiving externally applied address signals, wherein the address signal circuits have an address signal pad and an address signal buffer; and a plurality of control signal circuits arranged adjacent to the data input/output circuits of the first group and between the subset of memory cell blocks corresponding to the first group of data input/output circuits, wherein the control signal circuits have a control signal pad and a control signal buffer, and the semiconductor memory device is packed using a Non-Outer-DQ-Inner-Control (NON-ODIC) type package having a structure such that the data input/output pins of the data input/output circuits of the first group and the second group are collectively arranged adjacent to each other.

Claim 11

The semiconductor memory device according to claim 8, wherein a plurality of wires for electrically connecting the data input/output, address signal and control signal pads to corresponding pins of the package are arranged in a multi layer structure.

Claim 12

A semiconductor memory device formed on a chip, comprising: a set of memory cell blocks arranged in rows and columns, wherein each memory cell block comprises a plurality of memory cells for storing data; and a plurality of data input/output circuits divided into a plurality of groups, wherein each group is associated with and disposed proximate to a corresponding subset of memory cell blocks, and includes a plurality of data input/output pins, the semiconductor memory device being packed using a Non-Outer-DQ-Inner-Control (NON-ODIC) type package having a structure such that the data input/output pins of the plurality of groups are collectively arranged adjacent to each other.

Claim 13

A semiconductor memory device formed on a chip, comprising: a set of memory cell blocks arranged in rows and columns, wherein each memory cell block comprises a plurality of memory cells for storing data; and a plurality of data input/output circuits divided into a plurality of groups, wherein each group is associated with and disposed proximate to a corresponding subset of memory cell blocks, and includes a plurality of data input/output pins, the semiconductor memory device being packed using a Non-Outer-DQ-Inner-Control (NON-ODIC) type package having a structure such that the data input/output pins of the plurality of groups are collectively arranged adjacent to each other.

Claim 14

The semiconductor memory device according to claim 10, further comprising a plurality of address signal circuits for receiving address signals.

Claim 15

The semiconductor memory device according to claim 11, wherein the address signal circuits are arranged between the groups of data input/output circuits.

Claim 16

The semiconductor memory device according to claim 10, wherein the data input/output circuits comprise a data input/output pad and a data input/output buffer.

Claim 17

The semiconductor memory device according to claim 10, wherein the package comprises a NON-ODIC type ball grip array package.

Claim 18

The semiconductor memory device according to claim 11, wherein the address signal circuits comprise an address signal pad and an address signal buffer.

Claim 19

The semiconductor memory device according to claim 11, further comprising a plurality of control signal circuits, each control signal circuit arranged adjacent to an associated group of data input/output circuits and between the memory cell blocks of the subset of memory cell blocks corresponding to the associated group of data input/output circuits.

Claim 20

The semiconductor memory device according to claim 16, wherein the control signal circuits comprise a control signal pad and a control signal buffer.

Claim 21

The semiconductor memory device according to claim 16, wherein the data input/output circuits comprise a data input/output pad and a data input/output buffer, the address signal circuits comprise an address signal pad and an address signal buffer, the control signal circuits comprise a control signal pad and a control signal buffer, and the semiconductor memory device further comprises a plurality of wires for electrically connecting the data input/output, address signal, and control signal pads to corresponding pins of the package, the wires being arranged in a multi layer structure.