US5995404A
Expired / Lapsed
US
⏱️ 0.0 years remaining
DRAM architecture with aligned data storage and bond pads
Assignee: Texas Instruments Inc
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Filing: 1997-07-11
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Granted: 1999-11-30
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Expires: 2017-07-11
Abstract
Abstract A DRAM memory device has bond pads, such as DQa through DQh, arranged along the length of the substrate in a certain order. The bond pads carry data signals to and from the device with each bond pad carrying the same data bit of every data word. Arrays of memory cells 1201, 1210 extend transverse of the bond pads and are arranged in pairs of columns 1212-1226. Data circuits 1242, 1244 transmit the data signals between the bond pads and arrays. The data circuits include data lines 1230-1236 extending between the bond pads and pairs of columns of arrays. Each data line extends from one bond pad to plural pairs of columns of arrays in a sequence the same certain order.
Inventors
- 👤 Masayuki Nakaumura
- 👤 Brent S. Haukness
- 👤 Takesada Akiba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:27
CPC Classifications
H; H10; H10B; H10B12/00; G; G11; G11C; G11C7/00; G11C7/10; G11C7/1072
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
197 words
A memory device comprising: a. a semiconductor substrate carrying plural bond pads, the bond pads extending along the substrate in a first direction, the bond pads carrying data signals to and from the device, the data signals being arranged in words of plural bits, each bond pad carrying one data bit of each word and the bond pads being arranged in a certain order; b. arrays of memory cells formed on and extending across the substrate, the arrays of memory cells storing the data signals carried to and from the device by the bond pads, the arrays of memory cells being arranged in banks that extend in the first direction in parallel with the bond pads, in each bank the arrays of memory cells being arranged in columns arranged transverse to the first direction and the columns being paired with one another; and c. data circuits transmitting the data signals between the bond pads and arrays, the data circuits including data lines extending between the bond pads and pairs of columns of arrays, each data line extending from one bond pad to plural pairs of columns of arrays in a sequence the same as the certain order.
Claim 2
Dependent Claim
197 words
A memory device comprising: a. a semiconductor substrate carrying plural bond pads, the bond pads extending along the substrate in a first direction, the bond pads carrying data signals to and from the device, the data signals being arranged in words of plural bits, each bond pad carrying one data bit of each word and the bond pads being arranged in a certain order; b. arrays of memory cells formed on and extending across the substrate, the arrays of memory cells storing the data signals carried to and from the device by the bond pads, the arrays of memory cells being arranged in banks that extend in the first direction in parallel with the bond pads, in each bank the arrays of memory cells being arranged in columns arranged transverse to the first direction and the columns being paired with one another; and c. data circuits transmitting the data signals between the bond pads and arrays, the data circuits including data lines extending between the bond pads and pairs of columns of arrays, each data line extending from one bond pad to plural pairs of columns of arrays in a sequence the same as the certain order.
Claim 3
Dependent Claim
23 words
The memory device of claim 1 in which the bond pads are arranged in a line along the central axis of the substrate.
Claim 4
Dependent Claim
23 words
The memory device of claim 1 in which each data line extends from one bond pad to four pairs of columns of arrays.
Claim 5
Dependent Claim
29 words
The memory device of claim 1 in which plural data lines extend to each pair of columns of arrays in a particular arrangement the same as the certain order.
Claim 6
Dependent Claim
23 words
The memory device of claim 4 in which four data lines extend to each pair of columns of arrays in the particular arrangement.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-11-29 | 2003-05-31 | 2003-11-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-11-29 | 2007-05-31 | 2007-11-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-11-29 | 2011-05-31 | 2011-11-30 | $7700.00 | Window Closed / Lapsed |