US5724281A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor integrated circuit having improved wiring in input terminal
Assignee: Toshiba Corp
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Filing: 1997-01-29
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Granted: 1998-03-03
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Expires: 2017-01-29
Abstract
Abstract The input pads DQ0 to DQ3 and the input buffers DIB0 to DIB3 are connected to each other by means of the wires La or Lb. In the case where the memory cell array is of the ×4 bit pattern, the input pads DQ0 to DQ3 are connected to the input terminals of the input buffers DIB0 to DIB3, respectively, via the wires La, whereas in the case where the memory cell array is of the ×1 bit pattern, one of the input pads, that is, DQ0 is connected to each of the input terminals of the input buffers DIB0 to DIB3 via the wires Lb. The structures from the input buffers DIB0 to DIB3 to the memory cell arrays are the same and common to the ×4 bit pattern and the ×1 bit pattern, and therefore an increase in the driving performance of the transistors in the input buffers DIB0 to DIB3 can be suppressed.
Inventors
- 👤 Katsushi Nagaba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:56
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C7/00; G11C7/10; G11C7/1006
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
106 words
A semiconductor integrated circuit comprising: a plurality of terminals for inputting/outputting signals; a plurality of buffer circuits arranged to correspond to said plurality of terminals; a plurality of transmission paths for transmitting signals, to which said plurality of buffer circuits are respectively connected, said plurality of transmission paths being connected to a selected memory cell; and a plurality of wires for connecting at least one of said plurality of terminals to said plurality of buffer circuits, a position of the wire for connecting said at least one terminal to said plurality of buffer circuits being changed in accordance with a bit pattern of said memory cell.
Claim 2
Dependent Claim
106 words
A semiconductor integrated circuit comprising: a plurality of terminals for inputting/outputting signals; a plurality of buffer circuits arranged to correspond to said plurality of terminals; a plurality of transmission paths for transmitting signals, to which said plurality of buffer circuits are respectively connected, said plurality of transmission paths being connected to a selected memory cell; and a plurality of wires for connecting at least one of said plurality of terminals to said plurality of buffer circuits, a position of the wire for connecting said at least one terminal to said plurality of buffer circuits being changed in accordance with a bit pattern of said memory cell.
Claim 3
Dependent Claim
29 words
A circuit according to claim 1, wherein a current driving performance of said plurality of buffer circuits is set to a current driving performance of a maximum bit pattern.
Claim 4
Dependent Claim
18 words
A circuit according to claim 1, wherein said wire is positioned uppermost portion of said semiconductor integrated circuit.
Claim 5
Dependent Claim
24 words
A circuit according to claim 1, wherein said wire is a wire formed in a final step of manufacture of said semiconductor integrated circuit.
Claim 6
Dependent Claim
14 words
A circuit according to claim 1, wherein said plurality of terminals are input terminals.
Claim 7
Dependent Claim
33 words
A circuit according to claim 1, further comprising a plurality of write circuits connected respectively to said plurality of transmission paths, said plurality of write circuits writing data in said selected memory cell.
Claim 8
Dependent Claim
112 words
A semiconductor integrated circuit comprising: a plurality of input terminals for receiving input signals; a plurality of buffer circuits arranged to correspond to said plurality of input terminals; a decoder, to which output terminals of said plurality of buffer circuits are connected, for decoding said input signals supplied via said plurality of buffer circuits; circuit means selected in accordance with an output signal from said decoder; and at least one wire for connecting at least one of said plurality of input terminals to at least one of said plurality of buffer circuits, a position of said at least one wire being changed in accordance with the number of said circuit means selected.
Claim 9
Dependent Claim
112 words
A semiconductor integrated circuit comprising: a plurality of input terminals for receiving input signals; a plurality of buffer circuits arranged to correspond to said plurality of input terminals; a decoder, to which output terminals of said plurality of buffer circuits are connected, for decoding said input signals supplied via said plurality of buffer circuits; circuit means selected in accordance with an output signal from said decoder; and at least one wire for connecting at least one of said plurality of input terminals to at least one of said plurality of buffer circuits, a position of said at least one wire being changed in accordance with the number of said circuit means selected.
Claim 10
Dependent Claim
43 words
A circuit according to claim 7, wherein said circuit means is made of a plurality of memory cell arrays which constitute a plurality of banks, and said decoder selects at least one of said plurality of banks in accordance with an input signal.
Claim 11
Dependent Claim
58 words
A circuit according to claim 7, wherein said circuit means is a memory cell array, said decoder is a row decoder for selecting a word line of said memory cell array, and a refresh cycle of said memory cell array is changed by changing a connection position of said wire connecting said input terminals to said buffer circuits.
Claim 12
Dependent Claim
140 words
A semiconductor integrated circuit comprising: a plurality of input terminals for receiving input signals; a plurality of buffer circuits arranged to correspond to said plurality of input terminals; a plurality of transmission paths to which output terminals of said plurality of buffer circuits are respectively connected; a plurality of write circuits, each having input terminals connected to said plurality of transmission paths, respectively, said plurality of write circuits writing signals supplied to said plurality of transmission paths into a selected memory cell; and at least one wire for connecting at least one of said plurality of terminals to said plurality of buffer circuits, said at least one wire being formed in an uppermost portion of said semiconductor integrated circuit, and a position of said at least one wire being changed in accordance with a bit pattern of said memory cell.
Claim 13
Dependent Claim
140 words
A semiconductor integrated circuit comprising: a plurality of input terminals for receiving input signals; a plurality of buffer circuits arranged to correspond to said plurality of input terminals; a plurality of transmission paths to which output terminals of said plurality of buffer circuits are respectively connected; a plurality of write circuits, each having input terminals connected to said plurality of transmission paths, respectively, said plurality of write circuits writing signals supplied to said plurality of transmission paths into a selected memory cell; and at least one wire for connecting at least one of said plurality of terminals to said plurality of buffer circuits, said at least one wire being formed in an uppermost portion of said semiconductor integrated circuit, and a position of said at least one wire being changed in accordance with a bit pattern of said memory cell.
Claim 14
Dependent Claim
29 words
A circuit according to claim 10, wherein a current driving performance of said plurality of buffer circuits is set to a current driving performance of a maximum bit pattern.
Claim 15
Dependent Claim
27 words
A circuit according to claim 10, wherein said at least one wire is a wire formed in a final step of manufacture of said semiconductor integrated circuit.
Claim 16
Dependent Claim
123 words
A semiconductor integrated circuit comprising: a plurality of input terminals for receiving address signals; a plurality of buffer circuits arranged to correspond to said plurality of input terminals; a decoder, to which output terminals of said plurality of buffer circuits are connected, for decoding said address signals supplied via said plurality of buffer circuits; memory cell arrays selected in accordance with an output signal from said decoder, each of said memory cell arrays constituting a bank; and at least one wire for connecting at least one of said plurality of input terminals to at least one of said plurality of buffer circuits, a position of said at least one wire being changed in accordance with the bank pattern of said memory cell array.
Claim 17
Dependent Claim
123 words
A semiconductor integrated circuit comprising: a plurality of input terminals for receiving address signals; a plurality of buffer circuits arranged to correspond to said plurality of input terminals; a decoder, to which output terminals of said plurality of buffer circuits are connected, for decoding said address signals supplied via said plurality of buffer circuits; memory cell arrays selected in accordance with an output signal from said decoder, each of said memory cell arrays constituting a bank; and at least one wire for connecting at least one of said plurality of input terminals to at least one of said plurality of buffer circuits, a position of said at least one wire being changed in accordance with the bank pattern of said memory cell array.
Claim 18
Dependent Claim
29 words
A circuit according to claim 13, wherein a current driving performance of said plurality of buffer circuits is set to a current driving performance of a maximum bit pattern.
Claim 19
Dependent Claim
27 words
A circuit according to claim 13, wherein said at least one wire is a wire formed in a final step of manufacture of said semiconductor integrated circuit.
Claim 20
Dependent Claim
115 words
A semiconductor integrated circuit comprising: a plurality of input terminals for receiving address signals; a plurality of buffer circuits arranged to correspond to said plurality of input terminals; a row decoder, to which output terminals of said plurality of buffer circuits are connected, for decoding said address signals supplied via said plurality of buffer circuits; a memory cell selected in accordance with an output signal from said row decoder; and at least one wire for connecting at least one of said plurality of input terminals to at least one of said plurality of buffer circuits, a position of said at least one wire being changed in accordance with a refresh cycle of said memory cells.
Claim 21
Dependent Claim
115 words
A semiconductor integrated circuit comprising: a plurality of input terminals for receiving address signals; a plurality of buffer circuits arranged to correspond to said plurality of input terminals; a row decoder, to which output terminals of said plurality of buffer circuits are connected, for decoding said address signals supplied via said plurality of buffer circuits; a memory cell selected in accordance with an output signal from said row decoder; and at least one wire for connecting at least one of said plurality of input terminals to at least one of said plurality of buffer circuits, a position of said at least one wire being changed in accordance with a refresh cycle of said memory cells.
Claim 22
Dependent Claim
29 words
A circuit according to claim 16, wherein a current driving performance of said plurality of buffer circuits is set to a current driving performance of a maximum bit pattern.
Claim 23
Dependent Claim
27 words
A circuit according to claim 16, wherein said at least one wire is a wire formed in a final step of manufacture of said semiconductor integrated circuit.
References Cited (Backward Citations)
US5471157A
Cited
US5615166A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-03-02 | 2001-09-01 | 2002-03-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-03-02 | 2005-09-01 | 2006-03-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-03-02 | 2009-09-01 | 2010-03-03 | $7700.00 | Window Closed / Lapsed |