US5930198A
Expired / Lapsed
US
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Memory having a plurality of external clock signal inputs
Assignee: Round Rock Research LLC
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Filing: 1997-10-29
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Granted: 1999-07-27
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Expires: 2017-10-29
Abstract
Abstract A method and apparatus for operating a synchronous memory from a plurality of external clock signals is described. By providing external system, read, and write clock signals, a memory is operated by delaying operational clock signals, such as read and write clock signals, with respect to a system clock signal in order to reduce the apparent access time of the synchronous memory and/or to increase setup time to the synchronous memory. The delay of the read and write clock signals with respect to the system clock signal may be accomplished through a phase-lock-loop or delay-lock-loop which is off-chip with respect to the integrated circuit synchronous memory. Delay circuitry may be employed for operating one or more than one synchronous memories.
Inventors
- 👤 Kevin J. Ryan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:28
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/222; G11C7/10; G11C7/1072
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
52 words
A random access memory, comprising: a plurality of input pins configured for receiving input signals originating external to said random access memory; at least one of said input pins for receiving a system clock input signal; and at least another one of said input pins for receiving a read clock input signal.
Claim 2
Dependent Claim
52 words
A random access memory, comprising: a plurality of input pins configured for receiving input signals originating external to said random access memory; at least one of said input pins for receiving a system clock input signal; and at least another one of said input pins for receiving a read clock input signal.
Claim 3
Dependent Claim
23 words
The random access memory of claim 1, wherein said read clock input signal is phase-shifted with respect to said system clock input signal.
Claim 4
Dependent Claim
19 words
The random access memory of claim 2, wherein said random access memory is a synchronous dynamic random access memory.
Claim 5
Dependent Claim
52 words
A random access memory, comprising: a plurality of input pins configured for receiving input signals originating external to said random access memory; at least one of said input pins for receiving a system clock input signal; and at least another one of said input pins for receiving a write clock input signal.
Claim 6
Dependent Claim
52 words
A random access memory, comprising: a plurality of input pins configured for receiving input signals originating external to said random access memory; at least one of said input pins for receiving a system clock input signal; and at least another one of said input pins for receiving a write clock input signal.
Claim 7
Dependent Claim
23 words
The random access memory of claim 4, wherein said write clock input signal is phase-shifted with respect to said system clock input signal.
Claim 8
Dependent Claim
19 words
The random access memory of claim 5, wherein said random access memory is a synchronous dynamic random access memory.
Claim 9
Dependent Claim
65 words
A random access memory, comprising: a plurality of input pins configured for receiving input signals originating external to said random access memory; a first one of said input pins for receiving a system clock input signal; a second one of said input pins for receiving a read clock input signal; and a third one of said input pins for receiving a write clock input signal.
Claim 10
Dependent Claim
65 words
A random access memory, comprising: a plurality of input pins configured for receiving input signals originating external to said random access memory; a first one of said input pins for receiving a system clock input signal; a second one of said input pins for receiving a read clock input signal; and a third one of said input pins for receiving a write clock input signal.
Claim 11
Dependent Claim
30 words
The random access memory of claim 7, wherein said read clock input signal and said write clock input signal are each phase-shifted with respect to said system clock input signal.
Claim 12
Dependent Claim
19 words
The random access memory of claim 8, wherein said random access memory is a synchronous dynamic random access memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-07-26 | 2003-01-25 | 2003-07-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-07-26 | 2007-01-25 | 2007-07-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-07-26 | 2011-01-25 | 2011-07-27 | $7700.00 | Window Closed / Lapsed |