Digital display unit of a computer system having an improved method and apparatus for sampling analog display signals

Claim 3

The method of claim 1, further comprising the step of passing said pixel data elements corresponding to the same pixel position through a low-pass filter such that a pixel intensity corresponding to the average value of said pixel data elements is displayed on said display screen.

Claim 4

The method of claim 1, wherein step (e) comprises the step of phase delaying said intermediate clock signal once for each horizontal line included in said plurality of image frames.

Claim 5

The method of claim 1, wherein step (e) comprises the step of phase delaying said intermediate clock signal once for each of said plurality of image frames.

Claim 6

The method of claim 1, wherein the modulation of step (e) is performed even when synchronization of step (b) is attained between said intermediate clock signal and said synchronization signals.

Claim 7

A circuit for generating a sampling clock signal for an analog to digital converter (ADC) in a digital display unit, said ADC being used to sample a display signal, wherein said display signal includes an analog display data and corresponding synchronization signals, wherein each of a plurality of portions of said analog display data encodes a pixel data element value included in a plurality of pixel data element values, said plurality of pixel data element values defining a corresponding image frame, said circuit comprising: a clock generator circuit for generating an intermediate clock signal synchronized with said synchronization signals, wherein said intermediate clock signal specifies a specific sampling point at which said ADC samples each of said plurality of portions of said analog display data to recover a corresponding pixel data element value; a modulation circuit for modulating said intermediate clock signal by a different phase delay amount for successive image frames of said analog display signal, such that said analog display data is sampled at different sampling points for the same pixel position in said successive image frames, wherein at least some of said different sampling points are different from said specific sampling point specified by said intermediate clock signal synchronized with said synchronization signals, wherein said modulation circuit comprises: a delay determination circuit for determining an amount of phase delay by which said intermediate clock is to be modulated, wherein said delay determination block comprises a programmable register for storing a number indicative of said amount of phase delay, and wherein said delay determination block receives a new number from a memory in response to a beginning of new image frame being received in said analog display signal, said delay determination block storing said new number in said programmable register such that said amount of phase delay is varied for each of said successive frames; and an adjustable delay block for modulating said intermediate clock signal by said amount of phase delay.

Claim 8

A circuit for generating a sampling clock signal for an analog to digital converter (ADC) in a digital display unit, said ADC being used to sample a display signal, wherein said display signal includes an analog display data and corresponding synchronization signals, wherein each of a plurality of portions of said analog display data encodes a pixel data element value included in a plurality of pixel data element values, said plurality of pixel data element values defining a corresponding image frame, said circuit comprising: a clock generator circuit for generating an intermediate clock signal synchronized with said synchronization signals, wherein said intermediate clock signal specifies a specific sampling point at which said ADC samples each of said plurality of portions of said analog display data to recover a corresponding pixel data element value; a modulation circuit for modulating said intermediate clock signal by a different phase delay amount for successive image frames of said analog display signal, such that said analog display data is sampled at different sampling points for the same pixel position in said successive image frames, wherein at least some of said different sampling points are different from said specific sampling point specified by said intermediate clock signal synchronized with said synchronization signals, wherein said modulation circuit comprises: a delay determination circuit for determining an amount of phase delay by which said intermediate clock is to be modulated, wherein said delay determination block comprises a programmable register for storing a number indicative of said amount of phase delay, and wherein said delay determination block receives a new number from a memory in response to a beginning of new image frame being received in said analog display signal, said delay determination block storing said new number in said programmable register such that said amount of phase delay is varied for each of said successive frames; and an adjustable delay block for modulating said intermediate clock signal by said amount of phase delay.

Claim 9

circuit of claim 6, wherein delay determination block generates a sequence of random numbers, wherein each of said random numbers is representative of said different phase delay.

Claim 10

The circuit of claim 7, wherein said delay determination block generates one of said sequence of numbers for every image frame.

Claim 11

The circuit of claim 7, wherein said delay determination block generates one of said sequence of numbers for every horizontal line of said plurality of image frames.

Claim 12

The circuit of claim 6, wherein said adjustable delay block comprises: an analog variable delay element coupled to receive said intermediate clock signal and generate said sampling signal; and an ADC for driving said analog variable delay element, said ADC receiving a sequence of numbers representing said amounts of phase delay, said generating an analog signal having an voltage proportional to each of said sequence of numbers, wherein said analog signal causes to delay said intermediate signal by an amount proportionate to said voltage to generate said sampling signal.

Claim 13

The circuit of claim 6, wherein said adjustable delay block comprises: a plurality of delay elements coupled in sequence, wherein a first one of said plurality of delay elements receives said intermediate signal and each of said plurality of delay elements generates an output comprising said intermediate signal delayed by a different time delay; and a multiplexor selecting one of said outputs of said plurality of delays elements under the control of said delay determination circuit to generate said sampling clock signal.

Claim 14

The circuit of claim 6, wherein said modulation circuit modulates said intermediate clock signal by said different phase delay amount for successive image frames even when said intermediate clock signal is synchronized with said synchronization signals.

Claim 15

A computer system, comprising: a central processing unit (CPU) coupled to a bus; a random access memory coupled to said bus; a graphics controller circuit receiving a plurality of pixel data element values from said CPU, said graphics controller circuit generating an analog display signal including an analog display data and corresponding synchronization signals, wherein each of a plurality of portions of said analog display data encodes a pixel data element value included in said plurality of pixel data element values, said plurality of pixel data element values defining a corresponding image frame, wherein a plurality of image frames are encoded in said analog display signal; a digital display unit coupled to said graphics controller circuit, said digital display unit for displaying said plurality of image frames, said digital display unit comprising: a digital display screen; a clock generator circuit for generating an intermediate clock signal synchronized with said synchronization signals; a modulation circuit for generating a sampling clock signal by modulating said intermediate clock signal by different phase delay amounts for successive image frames, wherein said modulation circuit comprises: a delay determination circuit for determining an amount of phase delay by which said intermediate clock is to be modulated, wherein said delay determination block comprises a programmable register for storing a number indicative of said amount of phase delay, and wherein said delay determination block receives a new number from a memory in response to a beginning of new image frame being received in said analog display signal, said delay determination block storing said new number in said programmable register such that said amount of phase delay is varied for each of said successive frames; and an adjustable delay block for modulating said intermediate clock signal by said amount of phase delay, an analog to digital converter (ADC) coupled to said modulation circuit, said ADC receiving said sampling clock and sampling said analog display data to generate a plurality of pixel data elements, wherein modulation by different phase delay amounts causes said ADC to sample said analog display data at different sampling points for the same pixel position in said successive image frames; and an interface for generating display signals on said digital display screen based on said plurality of pixel data elements.

Claim 16

A computer system, comprising: a central processing unit (CPU) coupled to a bus; a random access memory coupled to said bus; a graphics controller circuit receiving a plurality of pixel data element values from said CPU, said graphics controller circuit generating an analog display signal including an analog display data and corresponding synchronization signals, wherein each of a plurality of portions of said analog display data encodes a pixel data element value included in said plurality of pixel data element values, said plurality of pixel data element values defining a corresponding image frame, wherein a plurality of image frames are encoded in said analog display signal; a digital display unit coupled to said graphics controller circuit, said digital display unit for displaying said plurality of image frames, said digital display unit comprising: a digital display screen; a clock generator circuit for generating an intermediate clock signal synchronized with said synchronization signals; a modulation circuit for generating a sampling clock signal by modulating said intermediate clock signal by different phase delay amounts for successive image frames, wherein said modulation circuit comprises: a delay determination circuit for determining an amount of phase delay by which said intermediate clock is to be modulated, wherein said delay determination block comprises a programmable register for storing a number indicative of said amount of phase delay, and wherein said delay determination block receives a new number from a memory in response to a beginning of new image frame being received in said analog display signal, said delay determination block storing said new number in said programmable register such that said amount of phase delay is varied for each of said successive frames; and an adjustable delay block for modulating said intermediate clock signal by said amount of phase delay, an analog to digital converter (ADC) coupled to said modulation circuit, said ADC receiving said sampling clock and sampling said analog display data to generate a plurality of pixel data elements, wherein modulation by different phase delay amounts causes said ADC to sample said analog display data at different sampling points for the same pixel position in said successive image frames; and an interface for generating display signals on said digital display screen based on said plurality of pixel data elements.

Claim 17

The computer system of claim 13, wherein said digital display screen includes a plurality of pixels, wherein said digital display screen is designed to respond slowly to changes in color intensity on any of said plurality of pixels, wherein the resulting slow response causes said digital display screen to operate as a low pass filter such that a user perceives the average intensity corresponding to different sampled data element values generated for the sampled pixel position in said successive image frames.

Claim 18

The computer system of claim 13, wherein said modulation circuit modulates said intermediate clock signal by said different phase delay amount for successive image frames even when said intermediate clock signal is synchronized with said synchronization signals.