US5739867A — Method and apparatus for upscaling an image in bo…

Claim 1

Independent Claim 188 words

A method of upscaling a source image frame in both vertical and horizontal directions to generate a destination image frame, the source image frame including a plurality of source scan lines, with each of said plurality of source scan lines including a plurality of source pixel data, the destination image frame including a plurality of destination lines, each of said plurality of destination lines including a plurality of destination pixel data, said method comprising the steps of: (a) receiving said plurality of source pixel data included in said source image frame using a first clock signal; (b) generating a second clock signal; (c) upscaling said source image frame in both vertical and horizontal directions to generate said plurality of destination pixel data representative of said destination image frame; and (d) providing said plurality of destination pixel data representative of said destination image frame using said second clock signal, wherein said second clock signal is generated to have a clock period such that the time to provide said plurality of destination pixel data is equal to a period to receive said source pixel data in said source image frame.

Claim 2

Independent Claim 188 words

A method of upscaling a source image frame in both vertical and horizontal directions to generate a destination image frame, the source image frame including a plurality of source scan lines, with each of said plurality of source scan lines including a plurality of source pixel data, the destination image frame including a plurality of destination lines, each of said plurality of destination lines including a plurality of destination pixel data, said method comprising the steps of: (a) receiving said plurality of source pixel data included in said source image frame using a first clock signal; (b) generating a second clock signal; (c) upscaling said source image frame in both vertical and horizontal directions to generate said plurality of destination pixel data representative of said destination image frame; and (d) providing said plurality of destination pixel data representative of said destination image frame using said second clock signal, wherein said second clock signal is generated to have a clock period such that the time to provide said plurality of destination pixel data is equal to a period to receive said source pixel data in said source image frame.

Claim 3

Dependent Claim 60 words

The method of claim 1, wherein step (c) comprises the steps of: (e) writing said plurality of source pixel data received in step (a) into a line buffer; and (f) reading said plurality of source pixel data written in step (e) using said second clock signal, wherein some of said source pixel data are replicated to upscale said source image.

Claim 4

Dependent Claim 24 words

The method of claim 2, further comprising the step of: (g) interpolating the pixel data in said upscaled image to generate said destination image.

Claim 5

Dependent Claim 26 words

The method of claim 3, further comprising the step of storing the pixel data in said upscaled image in a FIFO between steps (f) and (g).

Claim 6

Dependent Claim 46 words

The method of claim 3, wherein step (g) comprises the further step of using at least a present scan line and a previous scan line for interpolation, wherein said present scan line and said previous scan line are included in said plurality of source scan lines.

Claim 7

Dependent Claim 25 words

The method of claim 5, wherein at least one of said source scan lines is used a plurality of times as a present scan line.

Claim 8

Dependent Claim 36 words

The method of claim 6, further comprising the step of providing a line qualifier signal to indicate when said at least one said source scan lines is to be used again as a present scan line.

Claim 9

Dependent Claim 33 words

The method of claim 7, further comprising the step of providing a pixel qualifier line to indicate when a pixel data provided in step (f) corresponds to a next source image pixel data.

Claim 10

Dependent Claim 44 words

The method of claim 1, wherein a source image includes one or more of said source image frames, and wherein a destination image corresponding to said source image is generated by generating a destination image frame corresponding to each of said source image frames.

Claim 11

Dependent Claim 20 words

The method of claim 2, wherein said second clock signal is locked to said first clock signal in a proportion.

Claim 12

Dependent Claim 69 words

The method of claim 10, wherein said proportion is equal to (Htotal -- src×Vtotal -- src)/(Htotal -- dst×Vtotal -- dst), wherein Htotal -- src and Htotal -- dst represent the total number of pixels in each source scan line and each destination line respectively, and Vtotal -- src and Vtotal -- dst represent the total number of lines in a source image frame and a destination image frame respectively.

Claim 13

Dependent Claim 191 words

A circuit for upscaling a source image in both vertical and horizontal directions to generate a destination image, the source image including a plurality of source scan lines, with each of said plurality of source scan lines including a plurality of source pixel data, the destination image including a plurality of destination lines, each of said plurality of destination lines including a plurality of destination pixel data, said circuit comprising: receiving means for receiving said plurality of source pixel data included in said source image using a first clock signal; clock means for providing a second clock signal; and upscaling means for upscaling said source image in both vertical and horizontal directions to generate an upscaled image, wherein said upscaled image includes a number of pixels equal to a number of destination pixels in said destination image, said upscaling means providing the pixel data corresponding to said upscaled image using said second clock signal, wherein said second clock signal has a clock period such that the time to provide the pixel data in said upscaled image is equal to a period to receive said source pixel data in said source image.

Claim 14

Dependent Claim 191 words

A circuit for upscaling a source image in both vertical and horizontal directions to generate a destination image, the source image including a plurality of source scan lines, with each of said plurality of source scan lines including a plurality of source pixel data, the destination image including a plurality of destination lines, each of said plurality of destination lines including a plurality of destination pixel data, said circuit comprising: receiving means for receiving said plurality of source pixel data included in said source image using a first clock signal; clock means for providing a second clock signal; and upscaling means for upscaling said source image in both vertical and horizontal directions to generate an upscaled image, wherein said upscaled image includes a number of pixels equal to a number of destination pixels in said destination image, said upscaling means providing the pixel data corresponding to said upscaled image using said second clock signal, wherein said second clock signal has a clock period such that the time to provide the pixel data in said upscaled image is equal to a period to receive said source pixel data in said source image.

Claim 15

Dependent Claim 76 words

The circuit claim 12, wherein said upscaling means comprises: a line buffer; writing means for writing said plurality of source pixel data into said line buffer; and reading means for reading said plurality of source pixel data in said line buffer, wherein some of the pixel data stored in said line buffer are replicated to provide said upscaled image, and wherein the pixel data corresponding to said upscaled image is provided using said second clock signal.

Claim 16

Dependent Claim 40 words

The circuit of claim 13, wherein said line buffer comprises a dual-ported memory, and wherein said read operations are initiated in a port different from a port into which the said writing means writes said plurality of source pixel data.

Claim 17

Dependent Claim 14 words

The circuit of claim 13, wherein said line buffer comprises a single ported RAM.

Claim 18

Dependent Claim 23 words

The circuit of claim 13, wherein said line buffer includes sufficient memory to store at least two source scan lines of pixel data.

Claim 19

Dependent Claim 30 words

The circuit of claim 13, further comprising an interpolator for interpolating the pixel data in said upscaled image to generate said plurality of pixel data corresponding to said destination image.

Claim 20

Dependent Claim 203 words

An upscaler circuit for upscaling a source image in both vertical and horizontal directions to generate a destination image, the source image including a plurality of source scan lines, with each of said plurality of source scan lines including a plurality of source pixel data, the destination image including a plurality of destination lines, each of said plurality of destination lines including a plurality of destination pixel data, said circuit comprising: a data synchronizer for receiving said plurality of source pixel data at a source frame rate using a source clock signal; a clock signal generator for generating a destination clock signal; a line buffer for receiving and storing said plurality of source pixel data using said destination clock signal; and a control block for causing said plurality of source pixel data to be read from said line buffer, said control circuit causing the generation of an upscaled image which is upscaled in both vertical and horizontal directions, wherein said upscaled image includes a same number of pixel data as the number of destination image pixel data in said destination image, wherein said destination clock signal has a clock period such that the source frame rate is equal to said destination frame rate.

Claim 21

Dependent Claim 203 words

An upscaler circuit for upscaling a source image in both vertical and horizontal directions to generate a destination image, the source image including a plurality of source scan lines, with each of said plurality of source scan lines including a plurality of source pixel data, the destination image including a plurality of destination lines, each of said plurality of destination lines including a plurality of destination pixel data, said circuit comprising: a data synchronizer for receiving said plurality of source pixel data at a source frame rate using a source clock signal; a clock signal generator for generating a destination clock signal; a line buffer for receiving and storing said plurality of source pixel data using said destination clock signal; and a control block for causing said plurality of source pixel data to be read from said line buffer, said control circuit causing the generation of an upscaled image which is upscaled in both vertical and horizontal directions, wherein said upscaled image includes a same number of pixel data as the number of destination image pixel data in said destination image, wherein said destination clock signal has a clock period such that the source frame rate is equal to said destination frame rate.

Claim 22

Dependent Claim 28 words

The upscaler circuit of claim 18, further comprising a pixel qualifier signal for indicating when a previous pixel data read from said line buffer is to be replicated.

Claim 23

Dependent Claim 63 words

The upscaler circuit of claim 19, further comprising an interpolator which uses at least a present scan line and a previous scan line for interpolation, wherein said present scan line and said previous scan line are included in said plurality of source scan lines, said interpolator using one of said plurality of source scan lines more than once as a present scan line.

Claim 24

Dependent Claim 23 words

The upscaler of claim 18, wherein said line buffer comprises a RAM with sufficient memory to store at least two source scan lines.

Claim 25

Independent Claim 186 words

A system for displaying an image, comprising: receiving means for receiving a source image and providing a plurality of source pixel data representative of said source image; an upscaler coupled to said receiving means, said upscaler upscaling said source image in both vertical and horizontal directions to generate a plurality of destination pixel data representative of a destination image, said upscaler comprising: a data synchronizer for receiving said plurality of source pixel data at a source frame rate using a source clock signal; a clock signal generator for generating a destination clock signal; a line buffer for receiving said plurality of source pixel data using said destination clock signal; and a control block to cause said plurality of source pixel data to be read from said line buffer, wherein said control block causes said upscaler to generate said destination image, said destination image being generated at a destination frame rate, wherein said destination clock signal has a clock period such that said source frame rate is equal to said destination frame rate; and a display screen for displaying said destination image at said destination frame rate.

Claim 26

Independent Claim 186 words

A system for displaying an image, comprising: receiving means for receiving a source image and providing a plurality of source pixel data representative of said source image; an upscaler coupled to said receiving means, said upscaler upscaling said source image in both vertical and horizontal directions to generate a plurality of destination pixel data representative of a destination image, said upscaler comprising: a data synchronizer for receiving said plurality of source pixel data at a source frame rate using a source clock signal; a clock signal generator for generating a destination clock signal; a line buffer for receiving said plurality of source pixel data using said destination clock signal; and a control block to cause said plurality of source pixel data to be read from said line buffer, wherein said control block causes said upscaler to generate said destination image, said destination image being generated at a destination frame rate, wherein said destination clock signal has a clock period such that said source frame rate is equal to said destination frame rate; and a display screen for displaying said destination image at said destination frame rate.

Claim 27

Dependent Claim 54 words

The system of claim 22, wherein said system comprises a computer system, said computer system further comprising: a central processing unit (CPU) for providing a command on a bus; a random access memory coupled to said bus; a graphics controller circuit for receiving a plurality of source pixel data representative of a source image.

Claim 28

Dependent Claim 18 words

The system of claim 23, wherein said upscaler is provided with said graphics controller as one integrated circuit.

Claim 29

Dependent Claim 14 words

The system of claim 23, wherein said upscaler is provided in a display unit.

Claim 30

Dependent Claim 13 words

The system of claim 25, wherein said display unit comprises a flat monitor.

Claim 31

Dependent Claim 12 words

The system of claim 22, wherein said system comprises a television system.

Claim 32

Dependent Claim 12 words

The system of claim 22, wherein said system comprises a video camera.

Claim 33

Dependent Claim 12 words

The system of claim 22, wherein said system comprises a digital camera.

Claim 34

Dependent Claim 179 words

A digital display device, comprising: receiving means for receiving a source image and providing a plurality of source pixel data representative of said source image; an upscaler coupled to said receiving means, said upscaler upscaling said source image in both vertical and horizontal directions to generate a plurality of destination pixel data representative of a destination image, said upscaler comprising: a data synchronizer for receiving said plurality of source pixel data at a source frame rate; a clock signal generator for generating a destination clock signal; a line buffer for receiving said plurality of source pixel data using said destination clock signal; and a control block to cause said plurality of source pixel data to be read from said line buffer, wherein said control block causes said upscaler to generate said destination image, said destination image being generated at a destination frame rate, wherein said destination clock signal has a clock period such that said source frame rate is equal to said destination frame rate; and a display screen for displaying said destination image at said destination frame rate.

Claim 35

Dependent Claim 179 words

A digital display device, comprising: receiving means for receiving a source image and providing a plurality of source pixel data representative of said source image; an upscaler coupled to said receiving means, said upscaler upscaling said source image in both vertical and horizontal directions to generate a plurality of destination pixel data representative of a destination image, said upscaler comprising: a data synchronizer for receiving said plurality of source pixel data at a source frame rate; a clock signal generator for generating a destination clock signal; a line buffer for receiving said plurality of source pixel data using said destination clock signal; and a control block to cause said plurality of source pixel data to be read from said line buffer, wherein said control block causes said upscaler to generate said destination image, said destination image being generated at a destination frame rate, wherein said destination clock signal has a clock period such that said source frame rate is equal to said destination frame rate; and a display screen for displaying said destination image at said destination frame rate.

Claim 36

Dependent Claim 33 words

The digital display device of claim 30, wherein said source image is received as analog display data, and wherein said digital display device generates a source clock for sampling said analog display data.

Claim 37

Dependent Claim 30 words

The digital display device of claim 30, wherein said source image is received using an externally generated source clock, and wherein said destination clock is locked to said source clock.

Claim 38

Dependent Claim 38 words

The method of claim 1, wherein said source image has a first aspect ratio and said destination image frame has a second aspect ratio, and wherein said first aspect ratio is not equal to said second aspect ratio.

Claim 39

Dependent Claim 31 words

The method of claim 33, wherein the number of lines in said plurality of destination lines is not equal to the number of lines in said plurality of source scan lines.

Claim 40

Dependent Claim 60 words

The method of claim 34, wherein step (c) comprises the steps of: (e) writing said plurality of source pixel data received in step (a) into a line buffer; and (f) reading said plurality of source pixel data written in step (e) using said second clock signal, wherein some of said source pixel data are replicated to upscale said source image.

Claim 41

Dependent Claim 36 words

The method of claim 1, further comprising the steps of: receiving said source image in the form of an analog signal; generating said first clock signal; and sampling said analog signal using said first clock signal.

Claim 42

Dependent Claim 43 words

The method of claim 36, wherein said first clock signal is generated with a frequency such that each source scan line in said source image is sampled a number of times equal to the number of destination pixel data in each destination line.

Claim 43

Dependent Claim 38 words

The circuit of claim 13, wherein said source image has a first aspect ratio and said destination image frame has a second aspect ratio, and wherein said first aspect ratio is not equal to said second aspect ratio.

Claim 44

Dependent Claim 31 words

The circuit of claim 38, wherein the number of lines in said plurality of destination lines is not equal to the number of lines in said plurality of source scan lines.

Claim 45

Dependent Claim 81 words

The circuit of claim 13, wherein said source image is received in the form of an analog signal, and wherein said circuit further comprises: means for generating said first clock signal; and means for sampling said analog signal using said first clock signal, wherein said first clock signal is generated with a frequency such that each source scan line in said source image is sampled a number of times equal to the number of destination pixel data in each destination line.

Claim 46

Dependent Claim 39 words

The upscaler circuit of claim 18, wherein said source image has a first aspect ratio and said destination image frame has a second aspect ratio, and wherein said first aspect ratio is not equal to said second aspect ratio.

Claim 47

Dependent Claim 32 words

The upscaler circuit of claim 41, wherein the number of lines in said plurality of destination lines is not equal to the number of lines in said plurality of source scan lines.

Claim 48

Dependent Claim 90 words

The upscaler circuit of claim 18, wherein said source image is received in the form of an analog signal, and wherein said upscaler circuit further comprises a second clock generator for generating said first clock signal, wherein said first clock signal is provided to a sampling circuit for sampling said analog signal, wherein said first clock signal is generated with a frequency such that each source scan line in said source image is sampled a number of times equal to the number of destination pixel data in each destination line.

Claim 49

Dependent Claim 38 words

The system of claim 22, wherein said source image has a first aspect ratio and said destination image frame has a second aspect ratio, and wherein said first aspect ratio is not equal to said second aspect ratio.

Claim 50

Dependent Claim 31 words

The system of claim 44, wherein the number of lines in said plurality of destination lines is not equal to the number of lines in said plurality of source scan lines.

Claim 51

Dependent Claim 89 words

The system of claim 22, wherein said source image is received in the form of an analog signal, and wherein said upscaler circuit further comprises a second clock generator for generating said first clock signal, wherein said first clock signal is provided to a sampling circuit for sampling said analog signal, wherein said first clock signal is generated with a frequency such that each source scan line in said source image is sampled a number of times equal to the number of destination pixel data in each destination line.

Claim 52

Dependent Claim 14 words

The method of claim 1, wherein said method is implemented in a computer system.

Claim 53

Dependent Claim 30 words

The method of claim 47, wherein signal data for said plurality of source scan lines is received on one path and the corresponding synchronization signals are received on another path.

Claim 54

Dependent Claim 85 words

The method of claim 48, wherein step(b) comprises the further step of locking said second clock signal to said first clock signal in a proportion equal to (Htotal -- src×Vtotal -- src)/(Htotal -- dst×Vtotal -- dst), wherein Htotal -- src and Htotal -- dst represent the total number of pixels in each source scan line and each destination line respectively, and Vtotal -- src and Vtotal -- dst represent the total number of lines in a source image frame and a destination image frame respectively.

Claim 55

Dependent Claim 27 words

The method of claim 2, wherein said line buffer comprises sufficient memory to store less than or equal to two of said plurality of source scan lines.

Claim 56

Dependent Claim 14 words

The circuit of claim 12, wherein said circuit is implemented in a computer system.

Claim 57

Dependent Claim 30 words

The circuit of claim 51, wherein signal data for said plurality of source scan lines is received on one path and the corresponding synchronization signals are received on another path.

Claim 58

Dependent Claim 27 words

The circuit of claim 13, wherein said line buffer comprises sufficient memory to store less than or equal to two of said plurality of source scan lines.

Claim 59

Dependent Claim 20 words

The circuit of claim 13, wherein said second clock signal is locked to said first clock signal in a proportion.

Claim 60

Dependent Claim 69 words

The circuit of claim 54, wherein said proportion is equal to (Htotal -- src×Vtotal -- src)/(Htotal -- dst×Vtotal -- dst), wherein Htotal -- src and Htotal -- dst represent the total number of pixels in each source scan line and each destination line respectively, and Vtotal -- src and Vtotal -- dst represent the total number of lines in a source image frame and a destination image frame respectively.

Claim 61

Dependent Claim 16 words

The upscaler circuit of claim 18, wherein said upscaler circuit is implemented in a computer system.

Claim 62

Dependent Claim 31 words

The upscaler circuit of claim 56, wherein signal data for said plurality of source scan lines is received on one path and the corresponding synchronization signals are received on another path.

Claim 63

Dependent Claim 28 words

The upscaler circuit of claim 19, wherein said line buffer comprises sufficient memory to store less than or equal to two of said plurality of source scan lines.

Claim 64

Dependent Claim 21 words

The upscaler circuit of claim 19, wherein said destination clock signal is locked to said source clock signal in a proportion.

Claim 65

Dependent Claim 70 words

The upscaler circuit of claim 59, wherein said proportion is equal to (Htotal -- src×Vtotal -- src)/(Htotal -- dst×Vtotal -- dst), wherein Htotal -- src and Htotal -- dst represent the total number of pixels in each source scan line and each destination line respectively, and Vtotal -- src and Vtotal -- dst represent the total number of lines in a source image frame and a destination image frame respectively.

Claim 66

Dependent Claim 20 words

The system of claim 23, wherein said destination clock signal is locked to said source clock signal in a proportion.

Claim 67

Dependent Claim 70 words

The system of claim 61, wherein said proportion is equal to (Htotal -- src×Vtotal -- src) (Htotal -- dst×Vtotal -- dst), wherein Htotal -- src and Htotal -- dst represent the total number of pixels in each source scan line and each destination line respectively, and Vtotal -- src and Vtotal -- dst represent the total number of lines in a source image frame and a destination image frame respectively.

Claim 68

Dependent Claim 30 words

The system of claim 23, wherein signal data for said plurality of source scan lines is received on one path and the corresponding synchronization signals are received on another path.

Claim 69

Dependent Claim 27 words

The system of claim 23, wherein said line buffer comprises sufficient memory to store less than or equal to two of said plurality of source scan lines.

Claim 70

Dependent Claim 18 words

The digital display device of claim 30, wherein said digital display device is implemented in a computer system.

Claim 71

Dependent Claim 32 words

The digital display device of claim 65, wherein signal data for said plurality of source scan lines is received on one path and the corresponding synchronization signals are received on another path.

Claim 72

Dependent Claim 22 words

The digital display device of claim 65, wherein said destination clock signal is locked to said source clock signal in a proportion.

Claim 73

Dependent Claim 71 words

The digital display device of claim 67, wherein said proportion is equal to (Htotal -- src×Vtotal -- src)/(Htotal -- dst×Vtotal -- dst), wherein Htotal -- src and Htotal -- dst represent the total number of pixels in each source scan line and each destination line respectively, and Vtotal -- src and Vtotal -- dst represent the total number of lines in a source image frame and a destination image frame respectively.

Claim 74

Dependent Claim 29 words

The digital display device of claim 30, wherein said line buffer comprises sufficient memory to store less than or equal to two of said plurality of source scan lines.

Claim 75

Dependent Claim 205 words

A computer system for displaying an image, said computer system comprising: a central processing unit (CPU) coupled to a bus; a random access memory coupled to said bus; receiving means coupled to said bus for receiving a source image and providing a plurality of source pixel data representative of said source image; an upscaler coupled to said receiving means, said upscaler upscaling said source image to generate a plurality of destination pixel data representative of a destination image, said upscaler comprising: a data synchronizer for receiving said plurality of source pixel data at a source frame rate using a source clock signal; a clock signal generator for generating a destination clock signal; a line buffer for receiving said plurality of source pixel data using said destination clock signal; and a control block to cause said plurality of source pixel data to be read from said line buffer, wherein said control block causes said upscaler to generate said destination image, said destination image being generated at a destination frame rate, wherein said destination clock signal has a clock period such that said source frame rate is equal to said destination frame rate; and a display screen for displaying said destination image at said destination frame rate.

Claim 76

Dependent Claim 205 words

A computer system for displaying an image, said computer system comprising: a central processing unit (CPU) coupled to a bus; a random access memory coupled to said bus; receiving means coupled to said bus for receiving a source image and providing a plurality of source pixel data representative of said source image; an upscaler coupled to said receiving means, said upscaler upscaling said source image to generate a plurality of destination pixel data representative of a destination image, said upscaler comprising: a data synchronizer for receiving said plurality of source pixel data at a source frame rate using a source clock signal; a clock signal generator for generating a destination clock signal; a line buffer for receiving said plurality of source pixel data using said destination clock signal; and a control block to cause said plurality of source pixel data to be read from said line buffer, wherein said control block causes said upscaler to generate said destination image, said destination image being generated at a destination frame rate, wherein said destination clock signal has a clock period such that said source frame rate is equal to said destination frame rate; and a display screen for displaying said destination image at said destination frame rate.

Claim 77

Dependent Claim 15 words

The computer system of claim 70, wherein said upscaler is provided in a graphics controller.

Claim 78

Dependent Claim 16 words

The computer system of claim 70, wherein said upscaler is provided in a digital display unit.

Claim 79

Dependent Claim 20 words

The computer system of claim 70, said destination clock signal is locked to said source clock signal in a proportion.

Claim 80

Dependent Claim 70 words

The computer system of claim 73, wherein said proportion is equal to (Htotal -- src×Vtotal -- src)/(Htotal -- dst×Vtotal -- dst), wherein Htotal -- src and Htotal -- dst represent the total number of pixels in each source scan line and each destination line respectively, and Vtotal -- src and Vtotal -- dst represent the total number of lines in a source image frame and a destination image frame respectively.

Claim 81

Dependent Claim 28 words

The computer system of claim 70, wherein said line buffer comprises sufficient memory to store less than or equal to two of said plurality of source scan lines.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	2001-04-13	2001-10-13	2002-04-14	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2005-04-13	2005-10-13	2006-04-14	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2009-04-13	2009-10-13	2010-04-14	$7700.00	Window Closed / Lapsed

Method and apparatus for upscaling an image in both horizontal and vertical directions

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